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ADM7008 octal ethernet 10/100m phy datasheet versi o n 1.3 infineon -admtek co ltd . c o m.tw inform atio n in th is do cu m e n t is p r ov id ed in conn ectio n with infin e o n -admtek co ltd pro d u c ts. in fi n e on- adm t e k c o l t d m a y m a ke c h an ges t o s p ec i f i cat i ons an d pr o duct de scri pt i o n s at any t i m e, wi t h o u t no t i ce. designers m u st not rely on t h e abse nc e or c h aracteristics of a n y feature s or i n st r u ct i o ns m a rked ?rese r ved? or ? u nde fi ne d ? . i n fi neo n - a dm t e k c o l t d rese rve s t h ese f o r f u t u re defi ni t i on a n d s h al l ha ve n o respon sib ility wh atso ev er fo r con f licts or i n co m p atib ili ties arising fro m fu ture ch ang e s t o th em the p r od uct s m a y cont ai n d e si gn defect s o r e r r o rs k n o w as e rrat a , whi c h m a y cause t h e p r od uct t o de vi at e fr om publ i s he d speci fi cat i o n s . c u r r e n t cha r acterized e rra ta are availabl e o n requ est. to ob tain latest doc um entation please c o ntact you local infi neon-admtek co ltd sales off i ce or v i sit in fin e on -ad m tek co lt d?s we bsi t e a t h ttp ://www.admtek . co m . tw *t hi rd - p art y b r an ds a n d nam e s are t h e pr o p e rt y of t h ei r res p ect i v e ow ne rs . ? copyright 2003 by admtek incorporat ed all rights reserved an infineon technologies company
infineon-admtek co ltd v1.3 about this manual intended audience infineon-admtek co ltd?s custom ers structure this data sheet contains 6 chapters chapter 1 product overview chapter 2 interface descrip tion chapter 3 function description chapter 4. register description chapter 5. electrical specification chapter 6. packaging revision history d a t e v e r s i o n c h a n g e 2 3 jan u a r y 2003 1.0 first release of ADM7008 28 oct obe r 2 0 03 1.1 updated chapters 2, 3, & 4 27 n o vem b er 20 0 3 1.2 updated chapter 2* 2 8 apr il 20 04 1.3 updated infineon infineon-admtek co ltd logo * detailed updates can be supplied on request. customer support infineon-admtek co ltd incorporated, 2f, no.2, li-hsin rd., science-based industrial park, hsinchu, 300, taiwan, r.o.c. sales information tel + 886-3-5788879 ADM7008 fax + 886-3-5788871
infineon-admtek co ltd v1.3 table of contents chapter 1 product overview ........................................................................................ 1-1 1 . 1 o v e r v i e w .......................................................................................................... 1 - 1 1 . 2 f e a t u r e s ............................................................................................................ 1 - 1 1 . 3 b l o c k diagram ................................................................................................. 1 - 2 1 . 4 a b b r e v i a t i o n s ................................................................................................... 1 - 3 1 . 5 c o n v e n t i o n s ..................................................................................................... 1 - 4 1.5.1 data lengths ............................................................................................ 1-4 1.5.2 register type descriptions ...................................................................... 1-4 1.5.3 pin type descriptions .............................................................................. 1-5 chapter 2 interface description ................................................................................... 2-1 2 . 1 p i n diagram ..................................................................................................... 2 - 1 2 . 2 p i n d e s c r i p t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.1 twisted pair interface, 32 pins ................................................................ 2-2 2.2.2 ground and power, 20 pins ..................................................................... 2-2 2.2.3 mode setting ............................................................................................ 2-2 2.2.4 clock input select .................................................................................... 2-3 2.2.5 clock input, 3 pins ................................................................................... 2-3 2.2.6 rmii/s m ii interface, 48 pins ................................................................... 2-3 2.2.7 atpg signals, 2 pins ............................................................................. 2-16 2.2.8 reset pin ................................................................................................ 2-16 2.2.9 control signals, 3 pins ........................................................................... 2-17 2.2.10 led interface, 2 pins ............................................................................. 2-17 2.2.11 regulator c ontrol, 2 pins ...................................................................... 2-17 chapter 3 function description ................................................................................... 3-1 3 . 1 10/100m phy block ....................................................................................... 3-2 3.1.1 100base-x module ................................................................................... 3-2 3.1.2 100base-tx receiver ............................................................................... 3-2 3.1.3 100base-tx transmitter .......................................................................... 3-7 3.1.4 1 0 0 b a s e - f x r e c e i v e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.1.5 100base-fx transmitter .......................................................................... 3-8 3.1.6 10base-t module ..................................................................................... 3-8 3.1.7 operation modes ..................................................................................... 3-8 3.1.8 manchester encoder/decoder ................................................................. 3-8 3.1.9 transmit driver and receiver ................................................................. 3-8 3.1.10 smart squelch .......................................................................................... 3-9 3.1.11 carrier sense ........................................................................................... 3-9 3.1.12 collision detection ................................................................................ 3-10 3.1.13 jabber function ..................................................................................... 3-10 3.1.14 link test function ................................................................................. 3-10 3.1.15 automatic l i nk polarity detection ........................................................ 3-11 3.1.16 clock synthesizer ................................................................................... 3-11 3.1.17 auto negotiation .................................................................................... 3-11 3.1.18 auto negotiation and speed configuration ........................................... 3-12 3 . 2 mac interface ............................................................................................... 3-13 ADM7008 i 3.2.1 reduced media indepen d ent interfa ce (rmii) ...................................... 3-13
infineon-admtek co ltd v1.3 3.2.2 r e c e i v e p a t h f o r 1 0 0 m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.2.3 r e c e i v e p a t h f o r 1 0 m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.2.4 transmit path for 100m ........................................................................ 3-15 3.2.5 transmit path for 10m .......................................................................... 3-15 3.2.6 serial and source synchronous medi a independent interface .............. 3-16 3.2.7 100m receive path ................................................................................ 3-17 3.2.8 10m receive path .................................................................................. 3-18 3.2.9 100m transmit path .............................................................................. 3-19 3.2.10 10m transmit path ................................................................................ 3-19 3 . 3 led display .................................................................................................. 3-20 3.3.1 single color led ................................................................................... 3-20 3.3.2 dual color led ..................................................................................... 3-21 3.3.3 serial output led status ...................................................................... 3-22 3 . 4 managem e nt register access ........................................................................ 3-22 3.4.1 preamble suppression ........................................................................... 3-22 3.4.2 reset operation ..................................................................................... 3-23 3 . 5 power managem e nt ....................................................................................... 3-24 3.5.1 medium detect power saving ................................................................ 3-24 3.5.2 transmit power saving .......................................................................... 3-24 3 . 6 voltage regulator .......................................................................................... 3-26 chapter 4 register description .................................................................................... 4-1 4 . 1 register mapping ............................................................................................. 4-1 4 . 2 register bit mapping ....................................................................................... 4-2 4.2.1 register #0h -- control register .............................................................. 4-2 4.2.2 register #1h ? status register ................................................................. 4-2 4.2.3 register #2h ? phy id register (002e) .................................................. 4-2 4.2.4 register #3h ? phy id register (cc11) ................................................. 4-2 4.2.5 register #4h ? advertisement register .................................................... 4-2 4.2.6 register #5h ? link partner ability r e gister ........................................... 4-2 4.2.7 r e g i s t e r # 6 h ? a u t o n e g o t i a t i o n e x p a n s i o n r e g i s t e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.8 register #7h ? # fh reserved .................................................................. 4-2 4.2.9 register #10h ? phy con figuration register .......................................... 4-2 4.2.10 register #11h ? 10m con figuration register .......................................... 4-3 4.2.11 register #12h ? 100m configuration register ........................................ 4-3 4.2.12 register #13h ? led con figuration register .......................................... 4-3 4.2.13 register #14h ? interrupt enable register .............................................. 4-3 4.2.14 register #16h ? phy ge neri c status register ......................................... 4-3 4.2.15 register #17h ? phy spe cifi c status register ......................................... 4-3 4.2.16 register #18h ? recommend value storage register ............................. 4-3 4.2.17 register #19h ? interrupt status register ................................................ 4-3 4.2.18 register #1d h ? receive error counter .................................................. 4-4 4.2.19 register #1eh ? chip id (8888 ) ............................................................... 4-4 4.2.20 register #1fh ?total interrupt status (only for port 0) .......................... 4-4 4 . 3 r e g i s t e r d e s c r i p t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.1 control (register 0h) ............................................................................... 4-4 ADM7008 ii 4.3.2 status (register 1h) .................................................................................. 4-6
infineon-admtek co ltd v1.3 4.3.3 phy identifier register (register 2h) ...................................................... 4-8 4.3.4 phy identifier register (register 3h) ...................................................... 4-8 4.3.5 advertisement (register 4h) ..................................................................... 4-8 4.3.6 auto negotiation link p a rtner ability (register 5h) ............................. 4-10 4.3.7 auto negotiation expansion regi ster (register 6h) .............................. 4-11 4.3.8 register reserved (register 7h-fh) ....................................................... 4-11 4.3.9 generic phy configuration register (register 10h) ............................ 4-11 4.3.10 phy 10m module configuration register (register 11h) .................... 4-12 4.3.11 phy 100m module control register (register 12h) ............................. 4-12 4.3.12 led configuration register (register 13h) .......................................... 4-13 4.3.13 interrupt enable register (register 14h) .............................................. 4-14 4.3.14 phy generic status register (register 16h) ......................................... 4-15 4.3.15 phy specific status register (register 17h) ......................................... 4-16 4.3.16 phy recommend value status register (register 18h) ........................ 4-17 4.3.17 interrupt status register (register 19h) ................................................ 4-18 4.3.18 receive error counter register (register 1dh) .................................... 4-18 4.3.19 chip id register (register 1fh) ............................................................ 4-19 4.3.20 per port interrupt and r evision id register (register 1eh) ................. 4-19 chapter 5 electrical s p ecification ................................................................................ 5-1 5 . 1 d c c h a r a c t e r i z a t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1 absolute maximum rating ....................................................................... 5-1 5.1.2 recommended operatin g condition s ...................................................... 5-1 5.1.3 dc electrical characteristic s for 3.3v operation .................................. 5-1 5 . 2 a c c h a r a c t e r i z a t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2.1 xi/osci (cr y stal/oscillator) timing ....................................................... 5-2 5 . 3 rmii tim i ng .................................................................................................... 5-3 5.3.1 refclk input timing (when refclk_sel is set to 1) ....................... 5-3 5.3.2 refclk output timing (when refclk_sel is set to 0) ..................... 5-4 5.3.3 rmii trans mit timing ............................................................................. 5-5 5.3.4 rmii receive timing ............................................................................... 5-6 5 . 4 smii clock tim i ng .......................................................................................... 5-7 5.4.1 refclk input timing (when refclk_sel is set to 1) - ..................... 5-7 5.4.2 refclk output timing (when refclk_sel is set to 1) ..................... 5-8 5.4.3 smii/ss_smii transmit timing ............................................................... 5-9 5.4.4 smii/ss_smii receive timing ............................................................... 5-10 5 . 5 serial managem e nt inte rface (mdc/mdio) timing .................................... 5-11 5 . 6 power on configuration tim i ng ................................................................... 5-12 c h a p t e r 6 p a c k a g i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 ADM7008 iii
infineon-admtek co ltd v1.3 list of figures figure 1-1 ADM7008 block diagram ............................................................................. 1-2 figure 2-1 ADM7008 pin assignm e nt ............................................................................ 2-1 figure 3-1 ADM7008 switch applicati on (10/100m tp mode) .................................... 3-1 figure 3-2 100base-x block di agram and data path ..................................................... 3-3 figure 3-3 10base-t block di agram and data path ..................................................... 3-10 figure 3-4 r m ii signal diagram ................................................................................... 3-13 figure 3-5 r m ii recep tion w ithout error .................................................................... 3-14 figure 3-6 1 0 m rmii receive diag ram ....................................................................... 3-14 figure 3-7 100m rmii transm it diagram .................................................................... 3-15 figure 3-8 10m rmii transm it diagram ...................................................................... 3-15 figure 3-9 s m ii signal diagram ................................................................................... 3-17 figure 3-10 ss_smii signal diagram ........................................................................... 3-17 figure 3-11 100m smii receive tim i ng diagram ....................................................... 3-17 figure 3-12 100m ss_smii receive tim i ng dia g ram ................................................. 3-17 figure 3-13 10m smii receive tim i ng diagram ......................................................... 3-18 figure 3-14 10m ss_smii receive tim i ng dia g ram ................................................... 3-18 figure 3-15 100m smii transm it tim i n g d i a g r a m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 figure 3-16 100m ss_smii transmit tim i ng diagram ............................................... 3-19 figure 3-17 10m smii t r ansm i t t i m i n g d i a g r a m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 figure 3-18 10m ss_smii transmit tim i ng diagram ................................................. 3-20 figure 3-19 stream led under rmii mode ................................................................. 3-22 figure 3-20 smi read operation .................................................................................. 3-23 figure 3-21 smi w r i t e o p e r a t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 figure 3-22 medium det ect power managem e n t f l o w c h a r t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 figure 3-23 low power link pulse duri ng tx for power managem e nt ...................... 3-26 figure 3-24 external pn p powe r transistor diagram .................................................. 3-27 figure 5-1 c r ystal/oscillator tim i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 figure 5-2 r e fclk input tim i ng .................................................................................. 5-3 figure 5-3 r e fclk ou tput tim i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 figure 5-4 r m ii transmit tim i ng ................................................................................... 5-5 figure 5-5 r m ii receive tim i ng .................................................................................... 5-6 figure 5-6 r e fclk input tim i ng .................................................................................. 5-7 figure 5-7 s m ii/ss_smii refc lk output tim i ng ...................................................... 5-8 figure 5-8 s m ii/ss_smii transm it tim i ng ................................................................... 5-9 figure 5-9 s m ii/ss_smii receiv e tim i ng ................................................................... 5-10 figure 5-10 serial managem e nt in terface (mdc/mdio) timing ................................ 5-11 figure 5-11 power on conf iguration tim i ng ............................................................... 5-12 ADM7008 iv
infineon-admtek co ltd v1.3 list of tables table 3-1 l ook-up table for translating 5b symbols into 4b nibbles. .......................... 3-5 table 3-2 c h annel configuration .................................................................................. 3-16 table 3-3 r eceive data encodi ng for smii/ss_smii m ode ........................................ 3-18 table 3-4 s p eed led display ....................................................................................... 3-20 table 3-5 d uplex led display ..................................................................................... 3-21 table 3-6 a c tivity/link led display ........................................................................... 3-21 table 3-7 s p eed led display ....................................................................................... 3-21 table 3-8 a c tivity/link led display ........................................................................... 3-21 table 5-1 electrical absolu te maximum rating ............................................................. 5-1 table 5-2 r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 table 5-3 d c electrical character istics for 3.3v operation ........................................... 5-1 table 5-4 crystal/osci llator tim i ng ................................................................................ 5-2 table 5-5 r e fclk input tim i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 table 5-6 r e fclk output tim i ng ................................................................................. 5-4 table 5-7 r m ii transmit tim i ng .................................................................................... 5-5 table 5-8 r m ii receive tim i ng ...................................................................................... 5-6 table 5-9 r e fclk input tim i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 table 5-10 smii/ss_s m ii refc lk output tim i ng ..................................................... 5-8 table 5-11 smii/ss_s m ii transmit tim i ng .................................................................. 5-9 table 5-12 smii/ss_s m ii receive tim i ng .................................................................. 5-10 table 5-13 serial managem e nt in terface (mdc/mdio) timing ................................. 5-11 table 5-14 power on conf iguration tim i ng ................................................................. 5-12 ADM7008 v
ADM7008 product overview chapter 1 pr oduct overview 1.1 overview the ADM7008 is a single chip eight port 10/1 00m phy, which is designed for today?s low cost and low power dual speed application. it supports eight auto sensing 10/100 mbps por ts with on-chip clock recovery and base line wander correction in cluding in tegrated mlt - 3 functionality for 100 mbps operation. it also supports manchester code c onverter with on chip clock recovery circuitry for 10 mbps functionality, provides red u ced mii (rmii), se rial mii (s mii) and s ource synchronous mii (ss_ smii) in terface to fac ilitate h i gh port count switch sys t em application and reduce the pin num ber sim u ltaneously. for today?s inform ation application (ia), a d m7008 also supports ?auto cross ove r detection ? f unction to e lim inate the techni cal barrier between networking and the end user. w ith the aid of this auto cross over detection function, plug-n- play features can be easily applied to ia relative products. the m a jor design goal for ADM7008 is to re duce the pow er consum ption and syste m radiation for the whole system . w ith the aid of this low power consumption and low radiation chip, fan and on-system power s upply can be rem oved to save the total m a nu facture cost and m a ke soho ap plication achievable. 1.2 features ? ? ? ? ? ? ? ? ? ? ? ?
ADM7008 product overview ? supports pecl interface for fiber connection. ? built-in 3.3 v to 1.8v regulato r control sign al. ? built- in clo c k generato r and power on reset signal to sav e system cost. ? 128 pqfp with 1.8v/3.3v power supply. ? support power saving function. ? support parallel/serial led output. 1.3 block diagram figure 1-1 adm7 008 block diagr a m infineon-admtek co ltd 1-2 po r t 0 po r t 1 ... po r t 7 clo c k g e ne ra t o r tw i s t e d pa i r in te r f a c e m a c in te r f a c e le d di sp l a y sm i r m ii /s m i i / ss _sm i i se r i a l / p a r a lle l le d md c / m d i o po w e r m anagem ent mi i au t o n egot i a ti on c abl e b r ok en de t e c t o r 100m m odul e 10m m odul e dr i v e r m i i r m i i m i i s s _ s m i i m i i s m i i v o l t age r egul at or
ADM7008 product overview 1.4 abbreviations ansi am erican national stan dards ins t itu t e ber bit erro r rate col collis ion crs carrier sense crsdv carrier sense and data valid ctl crystal dsp digita l sign al proces sor dupcol duplex and collis ion esd end of stream delim iter fefi far end fault indication fifo first in first out flp fast link pulse fx fiber ia inform ation application lfsr linear feed back shifter register llp low-power link pulse lnkact link and activity lvttl ttl level mac media access controller md medium detect mdc managem e nt data clock mdio managem e nt data input/output mii media ind e p e ndent in terface nrz none return to zero nrzi none return to zero inverter op operation c ode pcs physical coding sub-layer pecl pseudo em itter couple l ogic phy physical layer phyaddr phy address pma physical medium attachm e nt pmd physical medium dependent pnp a type of transistor pqfp plastic quad flat pack refcl k reference clock rf rem o te fault rmii reduced media indep e n d ent in terface rsmode rmii/smii/ss_smii mode select rxc receive clo c k rxd receive data rxdv receive data valid rxer receive data error infineon-admtek co ltd 1-3 rxn receive negative (anal og receive d i fferential signal)
ADM7008 product overview rxp receive pos itiv e (analo g rece ive dif f erentia l sig n al) rx_sync receive syn c hronous sdn signal detect negati ve (fiber signal detect) sdp signal detect positi ve (fiber signal detect) selfx select f i ber smi serial managem e nt interface smii serial media independent interface soho sm all offic e and hom e office sqe signal quality error ssd start of str e am delim iter ss_smii source synchronous me dia independent interface sync synchronous ta turn around tdr tim e domain reflectometry tp twisted pair tp-pmd twisted pair physical medium depe ndent ttl transistor transistor logic txc transm ission clock (m ii) txclk transm ission clock (smii/ss_sm ii) txd transm ission data txen transm ission enable txer transm ission error txn transm ission negative txp transm ission positive /j/k 5b signal to detec t the s t art of a f r ame /t/r 5b signal to detect the end of a fra m e 1.5 conventi ons 1.5.1 data lengths qword 64-bits dword 32-bits word 16-bits byte 8 bits nibble 4 bits 1.5.2 register type descriptions register typ e description ro read only r/ w read and write capable infineon-admtek co ltd 1-4 sc self -clea r in g ll latching low, unlatch on read
ADM7008 product overview lh latching high, unlatch on read cor clear on read 1.5.3 pin type descriptions pin type description i: input o: output i/o: bi-dire c tion a l od: open drain sche: schm itt trig ger pu: pull up infineon-admtek co ltd 1-5 pd: pull down
ADM7008 interf ace description chapter 2 interface description 2.1 pin diagram v c c 3 o c ont r v c c a d r xn0 v c c a d g n d o v c c 3 o vc cad vc cad vc cad vcc 3 o g n d o r x d 1 _ p 0/ s p d l e d _p 0 ( r e c _10m _ p 0) r xd0 _ p 0 / r x d_ p 0 ( t e s t s e l 0 ) c r s d v _p 0 ( s e l f x 0) t xd1 _ p 0 / l nk ac t _ p 0 t xd0 _ p 0 / t x d _ p 0 tx en _ p 0 / n a r e f c l k g n d i k s c an_ m ode s c an_ e n xi xo o l r t x v c c p l l 2 v c c a 2 tx p 0 rx p 0 adm 7 0 0 8 qf p 1 2 8 tx en _ p 6 / n a t xd0 _ p 6 / t xd_ p 6 t x d 1_p 6 / l n k a c t _p 6 ( r sm o d e 0 ) c r sd v _ p6 / n a ( d u a lled ) r x d 0 _ p 6 / r x d _ p 6 ( r e c _ 10m _p 6) r x d 1_p 6/ s p e e d _ l e d _p 6 tx en _ p 7 / n a t xd0 _ p 7 / t xd_ p 7 t x d 1_p 7 / l n k a c t _p 7 ( f x _ p aus e ) c r s dv_ p 7 ( e n _ aut om di x ) r xd0 _ p 7 / r x d_ p 7 ( r e c _ 10m _p 7) r x d 1_p 7/ s p e e d _ l e d _p 7 led _ c lk led _ d a t a re f c l k _ s e l rs t _ n g n d i k v c c 2 i k p hya ddr 1 r s m ode 1 v c c a 2 tx p 7 rx n 1 rx p 1 tx n 1 tx p 1 vc ca2 tx p 2 tx n 2 rx p 2 rx n 2 rx n 3 rx p 3 tx n 3 tx p 3 vc ca2 tx p 4 tx n 4 rx p 4 rx n 4 rx n 5 rx p 5 tx n 5 tx p 5 vc ca2 tx p 6 tx n 6 rx p 6 rx n 6 rx n 7 rx p 7 md c md i o t x e n _p 1/ n a t x d 0_p 1/ t x d _ p 1 tx d 1 _ p 1 / ln k a c t _ p 1 c r s d v_ p 1 / na ( s e l f x 1 ) r xd0 _ p 1 / r xd_ p 1 ( t e s t s e l 1 ) r x d 1_p 1/ s p d l e d _p 1 ( r e c _ 10m _ p 1) t x e n _p 2/ n a t x d 0_p 2/ t x d _ p 2 tx d 1 _ p 2 / ln k a c t _ p 2 c r sd v _ p2 ( f x d u pl e x ) r x d0 _ p 2 / r x d_ p 2 ( p hy addr 0 ) r x d 1_p 2/ s p d l e d _p 2 ( r e c _ 10m _ p 2) gn d i k v cc2 i k t x en _ p 3 / tx _ s y n c t x d 0_p 3/ t x d _ p 3 tx d 1 _ p 3 / ln k a c t _ p 3 c r s d v _ p 3 / r x_ s y nc ( t e s t s e l 2 ) r xd0 _ p 3 / r xd_ p 3 ( a n e nd i s ) r x d 1_p 3 / s p d l e d _p 3 ( r e c _ 10m _ p 3) gn d o t x e n _p 4/ t x _c l k t x d 0_p 4/ t x d _ p 4 tx d 1 _ p 4 / ln k a c t _ p 4 crs d v _ p 4 / rx c l k r x d0 _ p 4 / r x d_ p 4 ( t p d up l e x) r x d 1_p 4 / s p d l e d _p 4 ( r e c _ 10m _ p 4) gn d i k v cc2 i k t x e n _p 5/ n a t x d 0_p 5/ t x d _ p 5 tx d 1 _ p 5 / ln k a c t _ p 5 c r s dv_ p 5 / n a ( t p _ p aus e ) r x d0 _ p 5 / r x d_ p 5 ( p w s av e _ di s ) r x d 1_p 5 / s p d l e d _p 5 ( r e c _ 10m _ p 5) 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 6 7 5 4 3 2 1 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 4 5 4 4 4 3 4 2 4 1 4 0 3 9 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 100 101 102 11 1 11 8 11 7 11 6 11 5 11 4 11 3 11 2 11 9 12 0 12 3 12 2 12 1 12 8 12 7 12 6 12 5 12 4 11 0 10 9 10 8 10 7 10 6 10 5 10 4 10 3 g n d r c v t xn0 g n d r t t xn7 g n d r t g n drt g n drt g n drt g n drt g n drt g n drt figure 2-1 adm7 008 pin assignm ent infineon-admtek co ltd 2-1
ADM7008 interf ace description 2.2 pin description note: for those pins, which ha ve m u ltiple f unctions, p i n nam e is separated by slash (?/?). if not specified, all signals are default to digital signals. please refer to section ?1 .5.3 pin type descriptions ? for an explanation of pin abbrevia tion s . 2.2.1 tw isted pair interface, 32 pins pin # pin name ty p e des c ription 123, 5, 7, 17 19, 29, 31, 41 t x p [ 0 : 7 ] o , analog twi s ted pair tran smit out put positive. 124, 4, 8, 16 20, 28, 32, 40 t x n [ 0 : 7 ] o , analog twi s ted pair tran smit out put neg a tive. 126, 2, 10, 14 22, 26, 34, 38 rxp[0:7] i, analog twi s ted pair re ceive input positive. 127, 1, 11, 13 23, 25, 35, 37 rxn[0:7] i, analog twi s ted pair re ceive input negative. 2.2.2 ground and po w er, 20 pins pin # pin name ty p e des c ription 125, 3, 9, 15, 21, 27, 33, 39 g n d r t a n a l o g gro und analog g r ou nd pad 118, 128, 12, 24, 36 vcca d a n a l o g power analog 3.3v powe r 122, 6, 18, 30 , 42 v c c a 2 a n a l o g power analog 1.8v powe r 1 2 0 g n d r c v a n a l o g gro und analog g r ou nd used by cl ock gen e rato r modul e 1 2 1 v c c p l l 2 a n a l o g power analog 1.8v powe r used b y clock gen e r ator m odul e 58, 80 104 gn d o d i g i t a l gro und gro und u s e d by 3.3v i/o. 46, 72, 88, 112 gn d i k d i g i t a l gro und gro und u s e d by core. 57, 79 103 v c c 3 o d i g i t a l power 3.3v powe r u s ed by i/o 45, 71, 87 v c c 2 i k d i g i t a l power 1.8v powe r u s ed by core 2.2.3 mode setting pin # pin name ty p e des c ription 43 rsmode1 i, pd rmii and smii/ss_ smii mode select signal. dedi cate d input provid ed by adm7 008 to d e termin e the interfa c e: 0: smii or ss_smii interface (se e crs d v_p6 po we r on setting for more detail) 1: rmii interfac e infineon-admtek co ltd 2-2
ADM7008 interf ace description 2.2.4 clock inpu t select pin # pin name ty p e des c ription 48 refclk_se l i, pd xi/xo and re fclk cl ock sele ct sig nal. dedi cated in put provid ed by adm7 008 to d e termin e the clo ck sou r ce for adm70 08. 0: ADM7008 will use xi/xo as cl ock so urce for inte rnal clo c k generator. in this mod e , refclk (pin 111) will out put 50m hz clo ck in rmii mode (r smode1 is s e t to 1) and 125m hz clo c k in eithe r smii or ss_smii mode (rsm ode1 is s e t to 0) 1: ADM7008 will use the in put of refcl k (pin 111 ) a s the clock so urce for inte rnal clock ge ne ra tor. not e : that wh en rsmo de 1 is set to 1 (rmii mode ), the input of refclk should b e 50m hz; when rs mode1 i s se t to 0 (smii or ss_smii mode) the clo ck in pu t on refclk should be 125 mhz 2.2.5 clock inpu t, 3 pins pin # pin name ty p e pin descrip tion 115 xi/osci i, ctl cry s tal/oscill ator inp u t. refclk_se l = 0: 25m crystal/oscillat o r input. refclk_se l = 1: leave unconn ecte d 116 xo o, ctl cry s tal outpu t. when 25m o scill ator i s use d , this pin shoul d be left uncon ne cted. see xi/osci de scrip t ion above. 1 1 1 r e f c l k i / o , 16ma lvttl refe ren c e cl ock. functio n on this pin i s highly de pe nded u pon the setting on refclk _sel and rsm o de1: refc lk_se l rsmo de1 refc lk (di r e c tion/frequ ency ) 0 0 output/125 mhz 0 1 output/50 mhz 1 0 in put/125 m h z with maximu m 100p pm 1 1 in put/50 mhz with maximum 100p pm 2.2.6 rmii/smii interface, 48 pins infineon-admtek co ltd 2-3 pin # pin name ty p e pin descrip tion 51, 52 powe r on setting rec_10m _p 7, en_automdix rmii mode rxd[1:0]_p7 i/o, 8ma, pd/pu rec_10m: value on rxd1_p7 will b e latche d by adm700 8 duri ng po we r on re set a s port 7 10m re-comm and val ue. 0: recomme nd port 7 to operate in 100 m mode 1: recomme nd port 7 to operate in 10m mode a uto mdix enable sign al: value on rxd0_p 7 will be latched by adm70 08 du ring p o wer on reset as auto mdix functi on co ntrol sign al. 0: disa ble all port s ? auto mdix function. 1: enable all port s ? auto mdix function. port 7 rmii rec e ive data, rxd[1: 0]. rxd[1:0] are the po rt 7 output di-bits synchrono usl y to refclk. upon a s sert ion of crs dv_p7, rxd0 and rxd1 re main a t ?00? until valid data is output from the fifo onto rxd. ?01? o n rxd1 and rxd0 indicates the start of valid data. if a false ca rrie r or a symbol error i s dete c ted, rxd1 an d rxd0 are set to ?10? for the
ADM7008 interf ace description pin # pin name ty p e pin descrip tion infineon-admtek co ltd 2-4 smii/ss_smi i mode spdled_p7, smii_rxd_p 7 ss_smii mode spdled_p7, ss_smii_rxd_ p7 duration of the activity. note that in 100mb/s mod e rxd ca n cha nge o n ce per refclk cycle, whe r ea s in 10m b/s mode rxd mu st be held stea dy for 10 c o ns ecu t ive r e f c lk c y c l es . port 7 smii receive data. rxd0 for the desi gnate d p o rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to tx_clk (pin 7 8 ). in 100mb/ s mode , rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 7. port 7 ss_smii receive data. rxd0 for the de sign ated po rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to rxclk (pin 75 ). in 100mb/s mo de, rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 7. 5 3 p o w e r o n setting fx_pause rmii mode crs dv_p7 smii/ss_smi i mode n/a i, lvttl, pd o, 8ma fiber pause recommend value. value on this pin will be latche d by adm7 008 d u ri ng po we r on reset a s fibe r port (se e selfx powe r on setting for more detail) pause ca pab ility cont rol si gnal . 0: pause off for all fiber p o rts 1: pause o n for all fiber p o rts port 7 ca rrie r sense/ re cei v e data valid . crsdv_p7 assert s whe n the re ceive medium is non -idl e. the asse rtion of crs dv_p7 i s asyn ch ro no us to ref c l k . at the de-asse rtion of carrie r, crsdv_p7 de -a ssert s syn c hronou sly to refclk only on the first di-bit of rx d. if there is still data in the fifo not yet prese n ted onto rx d, then on th e se con d di-b it of rxd, crs dv_p7 i s asse rted synch r o nou sly to refclk. the toggling of crsdv_p 7 on the first and se con d di-bit contin ue s until all the data in the fifo is presente d onto rx d. crs dv_p7 i s asse rted for the durat io n of carrie r acti vity for a false carrie r e v ent. not used in s m ii/ss_smii mode 54, 55 rmii mode txd[1:0]_p7 smii mode lnkact_p7, smii_txd _ p7 i, ttl, pd port 7 rmii tran smit data, txd[1:0]. transmit data for po rt 7 input the di-bi t s that re tran smitted an d a r e drive n synchrono usl y to refclk. not e : that in 100m b/s mod e , txd can chang e on ce p e r refclk cycl e, whe r ea s in 10mb/s mo d e , txd must be held steady for 1 0 con s e c utiv e refclk cycl es. link a nd acti vity led/port 7 sm ii transmit data. txd0 for port 7 inputs the d a ta that is tra n smitted a nd is drive n syn c hro nou sly to tx_clk (pin 78). in 100mb/s mode, txd0 inputs a new 10- bit segm ent starting with s y nc. in 10m b/s mod e , txd0 mu st rep eat ea ch 1 0 -bit segme n t 10 times. txd1_p 7 act s a s port 7 link/a ctivity l e d in both smii and ss_smii mode. see led de scriptio n for more detail.
ADM7008 interf ace description pin # pin name ty p e pin descrip tion infineon-admtek co ltd 2-5 smii mode lnkact_p7, ss_smii_txd_p 7 link a nd acti vity led/port 7 ss_smii transmit data. txd0 for port 7 inp u ts the data that is tran smitted and is d r iven synchrono usl y to tx_clk (pin 7 8 ). in 100mb/ s mode , txd0 inputs a n e w 10-bit segm e n t starting with sync. in 10mb/s mode, txd0 must re peat e a ch 1 0 -bit se gment 10 tim e s. 5 6 r m i i m o d e txen_p7 smii/ss_smi i low i, ttl port 7 tran smit enable. tran smit ena b le for po rt 7 indicates that the di-bit on txd is val i d and it is dri v en synchron ously to refclk. tied to lo w. txen_p7 sho u ld be ti ed to low for norm a l ope ration. 59, 60 power on setting rec_10m _p 6, dua lled rmii mode rxd[1:0]_p6 smii mode spdled_p6, smii_rxd_p 6 ss_smii mode spdled_p6, ss_smii_rxd_ p6 i pd, pd, o, 8ma o, 8ma o, 8ma rec_10m: value on rxd1_p6 will b e latche d by adm700 8 duri ng po we r on re set a s port 6 10m re-comm and val ue. 0: recomme nd port 6 to operate in 100 m mode 1: recomme nd port 6 to operate in 10m mode dual colo r l e d mode. value on rxd0_p6 will b e latche d by adm70 08 du ring p o wer on reset to form led co ntrol sign al. value on thi s pin will affect the output value on seri al led output. 0: single col o r 3 bits/p ort se rial stream (default valu e) 1: dual colo r 3 bits/po r t serial stre am port 6 rmii rec e ive data, rxd[1: 0]. rxd[1:0] are the po rt 6 output di-bits synchrono usl y to refclk. upon a s sert ion of crs dv_p6, rxd0 and rxd1 re main a t ?00? until valid data is output from the fifo onto rxd. the st art of valid da ta is indicated by ?01? on rx d1 and rx d0. if a false ca rri e r or a symbol e r ror i s dete c ted, rxd1 an d rx d0 a r e set to ?10? for the duration of the activity. note that in 100mb/s mod e rxd ca n cha nge o n ce per refclk cycle, whe r ea s in 10m b/s mode rxd mu st be held stea dy for 1 0 c o ns ecu t ive r e f c lk c y c l es . port 6 smii receive data. rxd0 for the desi gnate d p o rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to tx_clk (pin 7 8 ). in 100mb/ s mode , rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 6. port 6 ss_smii receive data. rxd0 for the de sign ated po rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to rxclk (pin 75 ). in 100mb/s mo de, rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 6. 61 power on setting rsmo de0 i, lvttl, pd rmii/smii/ss _ smii configuration bit 0. value on thi s pin will be latch ed by adm700 8 du ring p o wer on reset as interface config uration bit 0. combi ned with rs mode1 (pin 43), thre e possibl e interface s are pro v ided by adm700 8 rsmode[1:0] interfac e
ADM7008 interf ace description pin # pin name ty p e pin descrip tion infineon-admtek co ltd 2-6 rmii mode crs dv_p6 smii/ss_smi i mode n/a o, 8ma 00 smii 01 ss_smii 1x rmii port 6 ca rrie r sense/ re cei v e data valid . crsdv_p6 assert s whe n the re ceive medium is non -idl e. the asse rtion of crs dv_p6 i s asyn ch ro no us to ref c l k . at the de-asse rtion of carrie r, crsdv_p6 de -a ssert s syn c hronou sly to refclk only on the first di-bit of rx d. if there is still data in the fifo not yet prese n ted onto rx d, then on th e se con d di-b it of rxd, crs dv_p6 i s asse rted synch r o nou sly to refclk. the toggling of crsdv_p 6 on the first and se con d di-bit contin ue s until all the data in the fifo is presente d onto rx d. crs dv_p6 i s asse rted for the durat io n of carrie r acti vity for a fals e carrier event. not used in s m ii/ss_smii mode 62, 63 rmii mode txd[1:0]_p6 smii mode lnkact_p6, smii_txd_p 6 ss_smii mode lnkact_p6, ss_smii_txd_p 6 i, lvttl, pd, pd port 6 rmii tran smit data, txd[1:0]. transmit data for po rt 6 input the di-bi t s that re tran smitted an d a r e drive n synchrono usl y to refclk. no te that in 100m b/s mod e , txd can cha nge o n ce p e r ref c lk cy cle, wherea s in 10 mb/s mod e , txd mu st be held ste ady for 10 c o ns ecu t ive r e f c lk c y c l es . link a nd acti vity led/port 6 sm ii transmit data. txd0 for port 6 inputs the d a ta that is tra n smitted a nd is drive n syn c hro nou sly to tx_clk (pin 78). in 100mb/s mode, txd0 inputs a new 10- bit segm ent starting with s y nc. in 10m b/s mod e , txd0 mu st rep eat ea ch 1 0 -bit segme n t 10 times. txd1_p 6 act s as po rt 6 link/activity led in both smii and ss_smii mode. see led description f o r mo re detail . link a nd acti vity led/port 6 ss_smii transmit data. txd0 for port 6 inp u ts the data that is tran smitted and is d r iven synchrono usl y to tx_clk (pin 7 8 ). in 100mb/ s mode , txd0 inputs a n e w 10-bit segm e n t starting with sync. in 10mb/s mode, txd0 must re peat e a ch 1 0 -bit se gment 10 tim e s. 64 rmii mode txen_p6 smii/ss_smi i low i, ttl port 6 tran smit enable. tran smit ena b le for po rt 6 indicates that the di-bit on txd is val i d and it is dri v en synchron ously to refc lk. tied to lo w. txen_p6 sho u ld be ti ed to low for norm a l ope ration in b o th smii and ss_smii mode. 65, 66 power on setting rec_10m _p 5, pwsave_di s i, pd, pd rec_10m: value on rxd1_p5 will b e latche d by adm700 8 duri ng po we r on re set a s port 5 10m re-comm and val ue. 0: recomme nd port 5 to operate in 100 m mode (def ault) 1: recomme nd port 5 to operate in 10m mode lower p o wer link pul s e fu nction (power saving, llp) disa ble. value on rxd1 will b e latche d by adm 7008 d u ri ng p o we r on re set as p ower savin g di sable si g nal. ( see lo wer p o we r lin k
ADM7008 interf ace description pin # pin name ty p e pin descrip tion infineon-admtek co ltd 2-7 rmii mode rxd[1:0]_p5 smii mode spdled_p5, smii_rxd_p 5 ss_smii mode spdled_p5, ss_smii_rxd_ p5 o, 8ma pulse fu nctio n description for more deta il) 0: power sav i ng enabl e 1: power sav i ng disable (default) port 5 rmii rec e ive data, rxd[1: 0]. rxd[1:0] are the po rt 5 output di-bits synchrono usl y to refclk. upon a s sert ion of crs dv_p5, rxd0 and rxd1 re main a t ?00? until valid data is output from the fifo onto rxd. ?01? o n rxd1 and rxd0 indicates the start of valid data. if a false ca rrie r or a symbol error i s dete c ted, rxd1 an d rxd0 are set to ?10? for the duration of the activity. note that in 100mb/s mod e rxd ca n cha nge o n ce per refclk cycle, whe r ea s in 10m b/s mode rxd mu st be held stea dy for 1 0 c o ns ecu t ive r e f c lk c y c l es . port 5 smii receive data. rxd0 for the desi gnate d p o rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to tx_clk (pin 7 8 ). in 100mb/ s mode , rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 5. port 5 ss_smii receive data. rxd0 for the de sign ated po rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to rxclk (pin 75 ). in 100mb/s mo de, rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 5. 67 power on setting tp_pause rmii mode crs dv_p5 smii/ss_smi i mode n/a i, lvttl, pu o, 8ma twi s ted pair pause reco mmend val u e. value on this pin will be latch ed by adm700 8 du ring p o wer on reset as twi s ted pai r port (se e selfx power o n setting for more d e tail) p ause capability control signal. 0: pause off for all twi s ted pair p o rts 1: pause o n for all twi s ted pair p o rts port 5 ca rrie r sense/ re cei v e data valid . crsdv_p5 assert s whe n the re ceive medium is non -idl e. the asse rtion of crs dv_p5 i s asyn ch ro no us to ref c l k . at the de-asse rtion of carrie r, crsdv_p5 de -a ssert s syn c hronou sly to refclk only on the first di-bit of rx d. if there is still data in the fifo not yet prese n ted onto rx d, then on th e se con d di-b it of rxd, crs dv_p5 i s asse rted synch r o nou sly to refclk. the toggling of crsdv_p 5 on the first and se con d di-bit contin ue s until all the data in the fifo is presente d onto rx d. crs dv_p5 i s asse rted for the durat io n of carrie r acti vity for a fals e carrier event. not used in s m ii/ss_smii mode 68, 69 rmii mode txd[1:0]_p5 i, ttl, port 5 rmii tran smit data, txd[1:0]. transmit data for po rt 5 inputs the di -bits that re tra n smitted a nd are d r iven synchrono usl y to refclk. n ote t hat in 100m b/s m od e, txd
ADM7008 interf ace description pin # pin name ty p e pin descrip tion infineon-admtek co ltd 2-8 smii mode lnkact_p5, smii_txd_p 5 ss_smii mode lnkact_p5, ss_smii_txd_p 5 pd synchrono usl y to refclk. note that in 100m b/s mod e , txd can cha nge o n ce p e r ref c lk cy cle, wherea s in 10 mb/s mod e , txd mu st be held ste ady for 10 c o ns ecu t ive r e f c lk c y c l es . link a nd acti vity led/port 5 sm ii transmit data. txd0 for port 5 inputs the d a ta that is tra n smitted a nd is drive n syn c hro nou sly to tx_clk (pin 78). in 100mb/s mode, txd0 inputs a new 10- bit segm ent starting with s y nc. in 10m b/s mod e , txd0 mu st rep eat ea ch 1 0 -bit segme n t 10 times. txd1_p 5 act s as po rt 5 link/activity led in both smii and ss_smii mode. see led description f o r mo re detail . link a nd acti vity led/port 5 ss_smii transmit data. txd0 for port 5 inp u ts the data that is tran smitted and is d r iven synchrono usl y to tx_clk (pin 7 8 ). in 100mb/ s mode , txd0 inputs a n e w 10-bit segm e n t starting with sync. in 10mb/s mode, txd0 must re peat e a ch 1 0 -bit se gment 10 tim e s. 70 rmii mode txen_p5 smii/ss_smi i low i, ttl port 5 tran smit enable. tran smit ena b le for po rt 5 indicates that the di-bit on txd is val i d and it is dri v en synchron ously to refc lk. smii/ss_smii mode. keep low fo r no rmal op eratio n. 73, 74 power on setting rec_10m _p 4, tp_duplex rmii mode rxd[1:0]_p4 smii mode spdled_p4, smii_rxd_p 4 i/o, 8ma, pd/pu rec_10m: value on rxd1_p4 will b e latche d by adm700 8 duri ng po we r on re set a s port 4 10m re-comm and val ue. 0: recomme nd port 4 to operate in 100 m mode 1: recomme nd port 4 to operate in 10m mode twi s ted pair dupl ex re co mmend val u e. value on rxd1 will be latch ed by adm700 8 du ring p o wer on reset as du pl ex re comm end v a lue for twi s t ed pai r interfa c e. 0: half dupl e x for all twiste d pair p o rts 1: full dupl ex for all twisted pair po rts port 4 rmii rec e ive data, rxd[1: 0]. rxd[1:0] are the po rt 4 output di-bits synchrono usl y to refclk. upon a s sert ion of crs dv_p4, rxd0 and rxd1 re main a t ?00? until valid data is output from the fifo onto rxd. ?01? o n rxd1 and rxd0 indicates the start of valid data. if a false ca rrie r or a symbol error i s dete c ted, rxd1 an d rxd0 are set to ?10? for the duration of the activity. note that in 100mb/s mod e rxd ca n cha nge o n ce per refclk cycle, whe r ea s in 10m b/s mode rxd mu st be held stea dy for 1 0 c o ns ecu t ive r e f c lk c y c l es . port 4 smii receive data. rxd0 for the desi gnate d p o rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to tx_clk (pin 7 8 ). in 100mb/ s mode , rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 4.
ADM7008 interf ace description pin # pin name ty p e pin descrip tion infineon-admtek co ltd 2-9 ss_smii mode spdled_p4, ss_smii_rxd_ p4 port 4 ss_smii receive data. rxd0 for the de sign ated po rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to rxclk (pin 75 ). in 100mb/s mo de, rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 4. 75 rmii mode crs dv_p4 smii mode n/a ss_smii mode rxc l k i, lvttl, pd o, 8ma port 4 ca rrie r sense/ re cei v e data valid . crsdv_p4 assert s whe n the re ceive medium is non -idl e. the asse rtion of crs dv_p4 i s asyn ch ro no us to ref c l k . at the de-asse rtion of carrie r, crsdv_p4 de -a ssert s syn c hronou sly to refclk only on the first di-bit of rx d. if there is still data in the fifo not yet prese n ted onto rx d, then on th e se con d di-b it of rxd, crs dv_p4 i s asse rted synch r o nou sly to refclk. the toggling of crsdv_p 4 on the first and se con d di-bit contin ue s until all the data in the fifo is presente d onto rx d. crs dv_p4 i s asse rted for the durat io n of carrie r acti vity for a fals e carrier event. not used in s m ii mode 125m hz re ceive clo ck. t h is pin a c ts a s 125 mhz re ceive cl ock whe n adm7 0 08 is p r og ram m ed to ss_smii mode. all ss_smii_rxd are syn c hronou s to the rising e dge of this clo c k. not e : that cl ock on this pin w ill not be active during power on re set due to p o we r on setting. 76, 77 rmii mode txd[1:0]_p4 smii mode lnkact_p4, smii_txd_p 4 ss_smii mode lnkact_p4, ss_smii_txd_p 4 i, ttl, pd port 4 rmii tran smit data, txd[1:0]. transmit data for po rt 4 inputs the di -bits that re tra n smitted a nd are d r iven synchrono usl y to refclk. no te that in 100m b/s mod e , txd can cha nge o n ce p e r ref c lk cy cle, wherea s in 10 mb/s mod e , txd mu st be held ste ady for 10 c o ns ecu t ive r e f c lk c y c l es . link a nd acti vity led/port 4 sm ii transmit data. txd0 for port 4 inputs the d a ta that is tra n smitted a nd is drive n syn c hro nou sly to tx_clk (pin 78). in 100mb/s mode, txd0 inputs a new 10- bit segm ent starting with s y nc. in 10m b/s mod e , txd0 mu st rep eat ea ch 1 0 -bit segme n t 10 times. txd1_p 4 act s as po rt 4 link/activity led in both smii and ss_smii mode. see led description f o r mo re detail . link a nd acti vity led/port 4 ss_smii transmit data. txd0 for port 4 inp u ts the data that is tran smitted and is d r iven synchrono usl y to tx_clk (pin 7 8 ). in 100mb/ s mode , txd0 inputs a n e w 10-bit segm e n t starting with sync. in 10mb/s mode, txd0 must re peat e a ch 1 0 -bit se gment 10 tim e s. 78 rmii mode txen_p4 smii mode tx_clk i, ttl port 4 tran smit enable. tran smit ena b le for po rt 4 indicates that the di-bit on txd is val i d and it is dri v en synchron ously to refc lk. smii 125mhz referen c e cl ock. in smii mode, this pi n acts a s 125m hz refe rence clo c k for all p ort s . all transmit an d re ceive
ADM7008 interf ace description pin # pin name ty p e pin descrip tion infineon-admtek co ltd 2-10 ss_smii mode txclk data (in c lu de tran smit enab le and receive data valid) sho u ld be synchrono us to the risin g e dge of this cl ock. ss_smii 125mhz tra n smi t clock. in ss_smii mode, this pin acts a s 12 5m hz tran smit cl ock for all po rts. txd and txen sho u ld be synch r o nou s to the risi ng ed g e of this clo c k. 81, 82 power on setting rec_10m _p 3, anendis rmii mode rxd[1:0]_p3 smii mode spdled_p3, smii_rxd_p 3 ss_smii mode spdled_p3, ss_smii_rxd_ p3 i/o, 8ma, pd pd rec_10m: value on rxd1_p3 will b e latche d by adm700 8 duri ng po we r on re set a s port 3 10m re-comm and val ue. 0: recomme nd port 3 to operate in 100 m mode 1: recomme nd port 3 to operate in 10m mode twi s ted pair dupl ex re co mmend val u e. value on rxd1 will be latch ed by adm700 8 du ring p o wer on reset as auto negotiatio n di sabl e re com m end valu e for twi s ted pai r interfa c e. 0: auto-neg otiation enabl e for all twiste d pair p o rts. 1: auto-neg otiation di sabl e for all twisted pair po rts port 3 rmii rec e ive data, rxd[1: 0]. rxd[1:0] are the po rt 3 output di-bits synchrono usl y to refclk. upon a s sert ion of crs dv_p3, rxd0 and rxd1 re main a t ?00? until valid data is output from the fifo onto rxd. the st art of valid da ta is indicated by ?01? on rx d1 and rx d0. if a false ca rri e r or a symbol e r ror i s dete c ted, rxd1 an d rx d0 a r e set to ?10? for the duration of the activity. note that in 100mb/s mod e rxd ca n cha nge o n ce per refclk cycle, whe r ea s in 10m b/s mode rxd mu st be held stea dy for 1 0 c o ns ecu t ive r e f c lk c y c l es . port 3 smii receive data. rxd0 for the desi gnate d p o rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to tx_clk (pin 7 8 ). in 100mb/ s mode , rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 3. port 3 ss_smii receive data. rxd0 for the de sign ated po rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to rxclk (pin 75 ). in 100mb/s mo de, rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 3. 83 power on setting testsel2 rmii mode crs dv_p3 i, pd o, 8ma indust r ial te st mode select 2. value on this pin will b e latche d by adm700 8 duri ng po we r on re set a s in dust r ial test mode sele ct bit 2. pull down for norm a l ope ra tion. for test mode, see test sel e ct 0 for more detail port 3 ca rrie r sense/ re cei v e data valid . crsdv_p3 assert s whe n the re ceive medium is non -idl e. the asse rtion of crs dv_p3 i s asyn ch ro no us to ref c l k . at the de-asse rtion of carrie r, crsdv_p3 de -a ssert s syn c hronou sly to refclk only on the first di-bit of rx d. if there is still data in the fifo not yet p rese nted onto r x d then on th e s e c on d d i b i to fr x d
ADM7008 interf ace description pin # pin name ty p e pin descrip tion infineon-admtek co ltd 2-11 smii mode n/a ss_smii mode rx_syn c not yet prese n ted onto rx d, then on th e se con d di-b it of rxd, crs dv_p3 i s asse rted synch r o nou sly to refclk. the toggling of crsdv_p 3 on the first and se con d di-bit contin ue s until all the data in the fifo is presente d onto rx d. crs dv_p3 i s asse rted for the durat io n of carrie r acti vity for a fals e carrier event. not used in s m ii mode ss_smii receive synchro n izatio n sign al. in ss_smii mode, this pin sets the bit stre am alignm ent of ss_smii_rxd for all port s . 84, 85 rmii mode txd[1:0]_p3 smii mode lnkact_p3, smii_txd_p 3 ss_smii mode lnkact_p3, ss_smii_txd_p 3 i, ttl, pd port 3 rmii tran smit data, txd[1:0]. transmit data for po rt 3 inputs the di -bits that re tra n smitted a nd are d r iven synchrono usl y to refclk. no te that in 100m b/s mod e , txd can cha nge o n ce p e r ref c lk cy cle, wherea s in 10 mb/s mod e , txd mu st be held ste ady for 10 c o ns ecu t ive r e f c lk c y c l es . link a nd acti vity led/port 3 sm ii transmit data. txd0 for port 3 inputs the d a ta that is tra n smitted a nd is drive n syn c hro nou sly to tx_clk (pin 78). in 100mb/s mode, txd0 inputs a new 10- bit segm ent starting with s y nc. in 10m b/s mod e , txd0 mu st rep eat ea ch 1 0 -bit segme n t 10 times. txd1_p 3 act s as po rt 3 link/activity led in both smii and ss_smii mode. see led description f o r mo re detail . link a nd acti vity led/port 3 ss_smii transmit data. txd0 for port 3 inp u ts the data that is tran smitted and is d r iven synchrono usl y to tx_clk (pin 7 8 ). in 100mb/ s mode , txd0 inputs a n e w 10-bit segm e n t starting with sync. in 10mb/s mode, txd0 must re peat e a ch 1 0 -bit se gment 10 tim e s. 86 rmii mode txen_p3 smii mode smii_sync ss_smii mode tx_sync i, ttl port 3 tran smit enable. tran smit ena b le for po rt 3 indicates that the di-bit on txd is val i d and it is dri v en synchron ously to refc lk. smii synchro n izatio n sign al. in sm ii mode, this pin sets the bit stre am align m ent of smii_txd an d smii_rxd for all port s . ss_smii transmit synch r onization sig nal. in ss_smii mode, this pin sets the bit stre am alignm ent of ss_smii_txd for all port s . 89, 90 power on setting rec_10m _p 2, phyaddr0 rmii mode i, pd, pd o, rec_10m: value on rxd1_p2 will b e latche d by adm700 8 duri ng po we r on re set a s port 2 10m re-comm and val ue. 0: recomme nd port 2 to operate in 100 m mode 1: recomme nd port 2 to operate in 10m mode phy address bit 0. value on rx d1 will be latched by adm70 08 du ring p o wer on reset as phy addre s s bit 0. com b ine d wit h phyad dr 1 (pin 44) to form phy addres s for adm70 08. see phyaddr1 de scri ptio n for more de tail port 2 rmii rec e ive data, rxd[1: 0]. rxd[1:0] are the po rt 2 output di bits synchrono usl y to refclk upo n a ssert i on of
ADM7008 interf ace description pin # pin name ty p e pin descrip tion infineon-admtek co ltd 2-12 rxd[1:0]_p2 smii mode spdled_p2, smii_rxd_p 2 ss_smii mode spdled_p2, ss_smii_rxd_ p2 8 m a o u t p u t di-bits synchrono usl y to refclk. upon a s sert ion of crs dv_p2, rxd0 and rxd1 re main a t ?00? until valid data is output from the fifo onto rxd. the st art of valid da ta is indicated by ?01? on rx d1 and rx d0. if a false ca rri e r or a symbol e r ror i s dete c ted, rxd1 an d rx d0 a r e set to ?10? for the duration of the activity. note that in 100mb/s mod e rxd ca n cha nge o n ce per refclk cycle, whe r ea s in 10m b/s mode rxd mu st be held stea dy for 1 0 c o ns ecu t ive r e f c lk c y c l es . port 2 smii receive data. rxd0 for the desi gnate d p o rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to tx_clk (pin 7 8 ). in 100mb/ s mode , rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 2. port 2 ss_smii receive data. rxd0 for the de sign ated po rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to rxclk (pin 75 ). in 100mb/s mo de, rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 2. 91 power on setting fx_duplex rmii mode crs dv_p2 smii/ss_smi i mode n/a i/o, 8ma pu dupl ex re co mmend val u e for fibe r port. value on this pin will be latch ed by adm700 8 du ring p o wer on reset as du pl ex re comm end v a lue for all fib e r po rts. 0: half duplex for all fiber p o rts. 1: full duplex for all fiber p o rts. port 2 ca rrie r sense/ re cei v e data valid . crsdv_p2 assert s whe n the re ceive medium is non -idl e. the asse rtion of crs dv_p2 i s asyn ch ro no us to ref c l k . at the de-asse rtion of carrie r, crsdv_p2 de -a ssert s syn c hronou sly to refclk only on the first di-bit of rx d. if there is still data in the fifo not yet prese n ted onto rx d, then on th e se con d di-b it of rxd, crs dv_p2 i s asse rted synch r o nou sly to refclk. the toggling of crsdv_p 2 on the first and se con d di-bit contin ue s until all the data in the fifo is presente d onto rx d. crs dv_p2 i s asse rted for the durat io n of carrie r acti vity for a fals e carrier event. not used in s m ii and ss_smii mode 92, 93 rmii mode txd[1:0]_p2 i, ttl, pd, pd port 2 rmii tran smit data, txd[1:0]. transmit data for po rt 2 inputs the di -bits that re tra n smitted a nd are d r iven synchrono usl y to refclk. no te that in 100m b/s mod e , txd can cha nge o n ce p e r ref c lk cy cle, wherea s in 10 mb/s mod e , txd mu st be held ste ady for 10 c o ns ecu t ive r e f c lk c y c l es . link a nd acti vit y led/port 2 smii transmit data. txd0 for p ort
ADM7008 interf ace description pin # pin name ty p e pin descrip tion infineon-admtek co ltd 2-13 smii mode lnkact_p2, smii_txd_p 2 ss_smii mode lnkact_p2, ss_smii_txd_p 2 2 inputs the d a ta that is tra n smitted a nd is drive n syn c hro nou sly to tx_clk (pin 78). in 100mb/s mode, txd0 inputs a new 10- bit segm ent starting with s y nc. in 10m b/s mod e , txd0 mu st rep eat ea ch 1 0 -bit segme n t 10 times. txd1_p 2 act s as po rt 2 link/activity led in both smii and ss_smii mode. see led description f o r mo re detail . link a nd acti vity led/port 2 ss_smii transmit data. txd0 for port 2 inp u ts the data that is tran smitted and is d r iven synchrono usl y to tx_clk (pin 7 8 ). in 100mb/ s mode , txd0 inputs a n e w 10-bit segm e n t starting with sync. in 10mb/s mode, txd0 must re peat e a ch 1 0 -bit se gment 10 tim e s. 94 rmii mode txen_p2 smii/ss_smi i low i, ttl port 2 tran smit enable. tran smit ena b le for po rt 2 indicates that the di-bit on txd is val i d and it is dri v en synchron ously to refc lk. not used. ti ed to low fo r normal op eration in smii/ss_smii mode. 95, 96 power on setting rec_10m _p 1, testsel1 rmii mode rxd[1:0]_p1 smii mode spdled_p1, smii_rxd_p 1 ss_smii mode spdled_p1, ss_smii_rxd_ p1 i/o, 8ma, pd pd rec_10m: value on rxd1_p1 will b e latche d by adm700 8 duri ng po we r on re set a s port 1 10m re-comm and val ue. 0: recomme nd port 1 to operate in 100 m mode 1: recomme nd port 1 to operate in 10m mode indust r ial te st mode select 1. value on rxd0_p1 will be latche d by adm7 008 d u ri ng po we r on reset a s indu strial test mode sele ct bit 1. pull down for n o rm al operation. for te st mode, see te st sele ct 0 for more detail port 1 rmii rec e ive data, rxd[1: 0]. rxd[1:0] are the po rt 1 output di-bits synchrono usl y to refclk. upon a s sert ion of crs dv_p1, rxd0 and rxd1 re main a t ?00? until valid data is output from the fifo onto rxd. the st art of valid da ta is indicated by ?01? on rx d1 and rx d0. if a false ca rri e r or a symbol e r ror i s dete c ted, rxd1 an d rx d0 a r e set to ?10? for the duration of the activity. note that in 100mb/s mod e rxd ca n cha nge o n ce per refclk cycle, whe r ea s in 10m b/s mode rxd mu st be held stea dy for 1 0 c o ns ecu t ive r e f c lk c y c l es . port 1 smii receive data. rxd0 for the desi gnate d p o rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to tx_clk (pin 7 8 ). in 100mb/ s mode , rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 1. port 1 ss_smii receive data. rxd0 for the de sign ated po rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to rxclk (pin 75 ). in 100mb/s mo de, rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi g nate d p ort is a c ted a s s p ee d status le d for
ADM7008 interf ace description pin # pin name ty p e pin descrip tion infineon-admtek co ltd 2-14 port 1. 97 power on setting selfx1 rmii mode crs dv_p1 smii/ss_smi i mode n/a i/o, 8ma pd fiber/t wi sted pair configurati on bit 1. value on rxd1 will be latche d by adm7 008 d u ri ng po we r on reset a s fiber/t wiste d pai r interfa c e conf iguration bit 1 . combine d with selfx0 (power on setting val ue on crs d v_p0) to pro g ram a d m70 08 into 4 different mod e s. 00: all port s a r e twi s ted po rts 01: only port 7 is fiber p o rt, and all the other p o rts a r e twisted port s . 10: only port 7 and po rt 6 are fibe r po rts, and all the other p o rt are twi s ted port 11: all port s a r e fiber p o rt s. port 1 ca rrie r sense/ re cei v e data valid . crsdv_p1 assert s whe n the re ceive medium is non -idl e. the asse rtion of crs dv_p1 i s asyn ch ro no us to ref c l k . at the de-asse rtion of carrie r, crsdv_p1 de -a ssert s syn c hronou sly to refclk only on the first di-bit of rx d. if there is still data in the fifo not yet prese n ted onto rx d, then on th e se con d di-b it of rxd, crs dv_p1 i s asse rted synch r o nou sly to refclk. the toggling of crsdv_p 1 on the first and se con d di-bit contin ue s until all the data in the fifo is presente d onto rx d. crs dv_p1 i s asse rted for the durat io n of carrie r acti vity for a fals e carrier event. not used in s m ii and ss_smii mode 98, 99 rmii mode txd[1:0]_p1 smii mode lnkact_p1, smii_txd_p 1 ss_smii mode lnkact_p1, ss_smii_txd_p 1 i, ttl, pd port 1 rmii tran smit data, txd[1:0]. transmit data for po rt 1 inputs the di -bits that re tra n smitted a nd are d r iven synchrono usl y to refclk. no te that in 100m b/s mod e , txd can cha nge o n ce p e r ref c lk cy cle, wherea s in 10 mb/s mod e , txd mu st be held ste ady for 10 c o ns ecu t ive r e f c lk c y c l es . link a nd acti vity led/port 1 sm ii transmit data. txd0 for port 1 inputs the d a ta that is tra n smitted a nd is drive n syn c hro nou sly to tx_clk (pin 78). in 100mb/s mode, txd0 inputs a new 10- bit segm ent starting with s y nc. in 10m b/s mod e , txd0 mu st rep eat ea ch 1 0 -bit segme n t 10 times. txd1_p 1 act s as po rt 1 link/activity led in both smii and ss_smii mode. see led description f o r mo re detail . link a nd acti vity led/port 1 ss_smii transmit data. txd0 for port 1 inp u ts the data that is tran smitted and is d r iven synchrono usl y to tx_clk (pin 7 8 ). in 100mb/ s mode , txd0 inputs a n e w 10-bit segm e n t starting with sync. in 10mb/s mode, txd0 must re peat e a ch 1 0 -bit se gment 10 tim e s. 100 rmii mode txen_p1 smii/ss_smi i i, ttl port 1 tran smit enable. tran smit ena b le for po rt 1 indicates that the di-bit on txd is val i d and it is dri v en synchron ously to refc lk.
ADM7008 interf ace description pin # pin name ty p e pin descrip tion infineon-admtek co ltd 2-15 low not used. ti ed to low fo r normal op eration in smii/ss_smii mode. 105, 106 power on setting rec_10m _p 0, testsel0 rmii mode rxd[1:0]_p0 smii mode spdled_p0, smii_rxd_p 0 ss_smii mode spdled_p0, ss_smii_rxd_ p0 i/o, 8ma, pd, pd rec_10m: value on rxd1_p0 will b e latche d by adm700 8 duri ng po we r on re set a s port 0 10m re-comm and val ue. 0: recomme nd port 0 to operate in 100 m mode 1: recomme nd port 0 to operate in 10m mode indust r ial te st mode select 0. value on rxd0_p1 will be latche d by adm7 008 d u ri ng po we r on reset a s indu strial test mode sele ct bit 0. pull down testsel [2:0] for norm a l ope ration. testsel mode 000: no rmal mode port 0 rmii rec e ive data, rxd[1: 0]. rxd[1:0] are the po rt 0 output di-bits synchrono usl y to refclk. upon a s sert ion of crs dv_p0, rxd0 and rxd1 re main a t ?00? until valid data is output from the fifo onto rxd. the st art of valid da ta is indicated by ?01? on rx d1 and rx d0. if a false ca rri e r or a symbol e r ror i s dete c ted, rxd1 an d rx d0 a r e set to ?10? for the duration of the activity. note that in 100mb/s mod e rxd ca n cha nge o n ce per refclk cycle, whe r ea s in 10m b/s mode rxd mu st be held stea dy for 1 0 c o ns ecu t ive r e f c lk c y c l es . port 0 smii receive data. rxd0 for the desi gnate d p o rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to tx_clk (pin 7 8 ). in 100mb/ s mode , rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 0. port 0 ss_smii receive data. rxd0 for the de sign ated po rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to rxclk (pin 75 ). in 100mb/s mo de, rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 0. 107 power on setting selfx0 rmii mode crs dv_p0 i/o, 8ma pd fiber/t wi sted pair configurati on bit 0. value on rxd1 will be latche d by adm7 008 d u ri ng po we r on reset a s fiber/t wiste d pai r interfa c e conf iguration bit 1 . combine d with selfx1 (power on setting val ue on crs d v_p1) to pro g ram a d m70 08 into 4 different mod e s. see selfx1 for more detail port 0 ca rrie r sense/ re cei v e data valid . crsdv_p0 assert s whe n the re ceive medium is non -idl e. the asse rtion of crs dv_p0 i s asyn ch ro no us to ref c l k . at the de-asse rtion of carrie r, crsdv_p0 de -a ssert s syn c hronou sly to refclk only on the first di-bit of rx d. if there is still data in the fifo not yet prese n ted onto rx d, then on th e se con d di-b it of rxd, crs dv_p0 i s asse rted synch r o nou sly to refclk. the tl i f c r s d v p 0 t h fi t d d d i bit t i
ADM7008 interf ace description pin # pin name ty p e pin descrip tion smii/ss_smi i mode n/a toggling of crsdv_p 0 on the first and se con d di-bit contin ue s until all the data in the fifo is presente d onto rx d. crs dv_p0 i s asse rted for the durat io n of carrie r acti vity for a fals e carrier event. not used in s m ii and ss_smii mode 108, 109 rmii mode txd[1:0]_p0 smii mode lnkact_p0, smii_txd_p 0 ss_smii mode lnkact_p0, ss_smii_txd_p 0 i, ttl, pd port 0 rmii trans m it data, txd[1:0]. transmit data for po rt 1 inputs the di -bits that re tra n smitted a nd are d r iven synchrono usl y to refclk. no te that in 100m b/s mod e , txd can cha nge o n ce p e r ref c lk cy cle, wherea s in 10 mb/s mod e , txd mu st be held ste ady for 10 c o ns ecu t ive r e f c lk c y c l es . link a nd acti vity led/port 0 sm ii transmit data. txd0 for port 0 inputs the d a ta that is tra n smitted a nd is drive n syn c hro nou sly to tx_clk (pin 78). in 100mb/s mode, txd0 inputs a new 10- bit segm ent starting with s y nc. in 10m b/s mod e , txd0 mu st rep eat ea ch 1 0 -bit segme n t 10 times. txd1_p 0 act s as po rt 0 link/activity led in both smii and ss_smii mode. see led description f o r mo re detail . link a nd acti vity led/port 0 ss_smii transmit data. txd0 for port 1 inp u ts the data that is tran smitted and is d r iven synchrono usl y to tx_clk (pin 7 8 ). in 100mb/ s mode , txd0 inputs a n e w 10-bit segm e n t starting with sync. in 10mb/s mode, txd0 must re peat e a ch 1 0 -bit se gment 10 tim e s. 110 rmii mode txen_p0 smii/ss_smi i low i, ttl port 0 tran smit enable. tran smit ena b le for po rt 0 indicates that the di-bit on txd is val i d and it is dri v en synchron ously to refc lk. not used. ti ed to low fo r normal op eration in smii/ss_smii mode. 2.2.7 atpg signals, 2 pins pin # pin name ty p e des c ription 1 1 4 s c a n _ e n i vlttl scan_e n: scan e nabl e for test 0: norm al mode pull low for n o rmal o p e r ati on 1 1 3 s c a n _ m o d e i vlttl scan_ m o d e: scan mod e sele ct for te st 0: norm al mode pull low for n o rmal o p e r ati on 2.2.8 reset pin infineon-admtek co ltd 2-16 pin # pin name ty p e des c ription 4 7 r e s e t # i , sche re set signal. active low to brin g adm7 008 into reset con d ition. re comm end ke eping lo w for at least 100 ms to ensure the st ability of the sy stem after power on reset.
ADM7008 interf ace description 2.2.9 control signals, 3 pins pin # pin name ty p e pin descrip tion 1 0 1 m d i o i / o , lvttl mana geme n t data. mdio tran sfers ma n agem ent data in and out of the device syn c h r o n ous to m dc. 1 0 2 m d c i , lvttl mana geme n t data referen c e cl ock. a non -continu o u s cl ock input for man agem ent usa ge. adm700 8 will use this clock to sam p le data i nput on m d io and d r ive d a ta onto mdi o acco rdin g to rising e dge of this clo c k. 4 4 p h y a d d r 1 i , lvttl phy addre ss bit 1. pure input of adm7 008. com b in ed with phyaddr0 to form the m o st significan t 2 bits of phy addre s s for ADM7008. the lsb 3 bits will be assigned by ADM7008 automati c ally acco rdin g to port num be r 000 port 0 001 port 1 010 port 2 011 port 3 100 port 4 101 port 5 110 port 6 111 port 7 2.2.10 led interface, 2 pins pin # pin name t y pe description 5 0 l e d _ c l k i/o, 4ma, pd led cl ock. non - contin u ous cloc k for serial output led status. the clock high d u ration is 40 n s and low fo r 6 00n s. this 6 40 n s p e rio d form s o ne clo c k cycl e and 24 clo c ks fo rm one le d burst. the first clock output is use d to latch the first bit on led_ data (see led_ data for more d e tail) a nd the final clo ck i s use d to latch the last data on led_dat a . led_ clk will be kept lo w for 40 m s befo r e next led stream data is outp u t. 4 9 l e d _ d a t a i/o, 4ma, pd led data. 8 port status o u tput with differe nce se que nce acco rdin g to different interf ace. data _l ed is drive n out by adm70 08 at the falling ed g e of clk_le d. system desig n sho u ld u s e th e risi ng ed ge of led_ clk to latch the da ta on led_ data. the outp u t se quen ce i s : dup co l0 (f irst bit output) ? du pc ol1 ? ? ? du pcol 7 ? speed0 ? speed1 ? ? ? spe ed7 ? ln kac t 0 ? lnkact1 ? ? ? lnkact7 (las t bit output) 2.2.11 regulator control, 2 pins infineon-admtek co ltd 2-17 pin # pin name ty p e des c ription 1 1 7 c o nt r o l o , analog reg u lato r co ntrol. voltage control to external 1.8v reg u lat o r. see 4.2.9 for more function d e scription.
ADM7008 interf ace description infineon-admtek co ltd 2-18 1 1 9 r t x i , analog con s tant volt age referen c e. external 1.1k ?
ADM7008 function description chapter 3 function description ADM7008 integrates eight 100base-x physical s ublayer (phy), 100base-tx physical m e dium dependent (pmd) transceivers, ei ght com p lete 10base-t modules in to a single chip for both 10 mbits/s and 100 mbits/s ethernet operation. it also supports 100base-fx operation through external fiber-optic transceivers. the devi ce is capable of operating in either full-duplex m o de or half-duplex mode in either 10 mbits/s or 100 mbits/s operation. oper ational m o des can be selected by hardware configuration pins, software settings of m a nagem e nt registers, or determ ined by t h e on-chip auto negotiation logic. the 10base-t section o f the device consists of th e 10 mbits/s transceiv e r m odule with filters and a manchester endec m o dule. figure 3-1 adm7 008 s w i t ch applica t ion (10/1 00m tp mode) ADM7008 consists of eight kinds of m a jor blocks: ? eight 10/100m phy bl ocks ? mac interface ? led display ? smi infineon-admtek co ltd 3-1 ? power managem e nt ad m 7008 50 / 1 2 5 m h z r m ii/ s m ii[ 0 ] r m ii/ s m i i [ 1 ] r mii/ s m ii[ 2 ] rm i i / s m ii[ 3 ] r m ii/ s m ii[ 4 ] r m ii/ s m ii[ 5 ] r m ii/ s m ii[ 6 ] rmii/ s m ii[ 7 ] t xp[ 0 ] / t xn [ 0 ] r x p [ 0 ] /r x n [0 ] t xp[ 0 ] / t xn [ 0 ] r x p [ 0 ] /r x n [0 ] t xp[ 0 ] / t xn [ 0 ] r x p [ 0 ] /r x n [0 ] t xp[ 0 ] / t xn [ 0 ] r x p [ 0 ] /r x n [0 ] t xp[ 0 ] / t xn [ 0 ] r x p [ 0 ] /r x n [0 ] t xp[ 0 ] / t xn [ 0 ] r x p [ 0 ] /r x n [0 ] t xp[ 0 ] / t xn [ 0 ] r x p [ 0 ] /r x n [0 ] t xp[ 0 ] / t xn [ 0 ] r x p [ 0 ] /r x n [0 ] re f c l k ma c ma c ma c ma c ma c ma c ma c ma c s w i t c h fabr i c rj - 4 5 ma g n e t i c s ma g n e t i c s rj - 4 5 rj -4 5 rj - 4 5 rj - 4 5 rj - 4 5 rj - 4 5 rj -4 5
ADM7008 function description ? ? ? ? ? ? ? ? ? ? ? ? ?
ADM7008 function description the receiv e r block consists of the following functional sub - blocks : ? a/d converter ? adaptive equalizer and tim i ng rec overy module ? nrzi/nrz and seria l/p arallel deco der ? descram b ler ? sym bol alignm ent block ? sym bol decoder ? collision de tect block ? carrier sense block ? stream dec oder block a/d converter high perform a nce a/d converter w ith 125m sampli ng rate converts signal s received on rxp/rxn pins to 6 b i ts da ta s t re a m s; besides it posses s au to-ga i n-co ntrol capab ility tha t will f u rthe r im prove receiv e perform a nce especially under long cable or harsh detrim ental si gn al in tegrity. due to high pass charac ter i stic on transf orm e r, built in base-line- wander corr ecting c i rcu i t will cance l it out and r e store its dc level. figure 3-2 1 00base -x bl ock diag ram and da ta pa th adaptive equalizer and timing recovery module all digital design is especial i mmune from noise environm ents and achieves better correlations between production and system testing. baud rate adaptive equalizer/tim ing recovery com p ensates infineon-admtek co ltd 3-3 m ii to s m ii c o n v e r t e r rx d 4b / 5 b d e c ode r de s c r a m b l e r s e ri a l - t o- p a r a l l el c l oc k/ da ta re c o v e ry a d a ptive eq u a l i ze r s m ii to m ii c o n v e r te r rx st a t e ma c h i n e sy n c r x d [ 3: 0] rx p rx n sd p bp _ d s c r cr s rx dv rx e r 1 0 0 b a s e - x re ce iv e r tx st a t e ma ch i n e 4b / 5 b dec ode r scr a m b l e r p a r a llal- t o - s e r i a l mlt - 3 st a t e mac h i n e 10/ 100 tx driver fi be r op t i c driver sy n c tx d co l tx c l k tx e n tx e r tx d [ 3 : 0 ] bp _ s c r tx p tx n tx p tx n 100b a s e - x t r a n s m i t t e r a/d b l o c k te s t m d nr zi t o 6 b nr z to nr z i fi b e r o p t i c r ece i v er rx p rx n
ADM7008 function description line loss induced from t w isted pair and tracks far end clock at 125m samples per second. adaptive equalizer implem e nted with feed forward and deci sion feedback techniques m eet the requirement of ber less than 10-12 for transm ission on cat5 t w is ted pair cable ranging from 0 to 140 m e ters. nrzi/nrz and serial/parallel decoder the recovered data is converted fro m nrzi to nrz. the data is not necessarily aligned to 4 b /5b code group?s boundary. data descrambling the descrambler acquires synchronization with the data stream by recognizing idle bursts of 40 or more bits and locking its deciphering linear fee dback shif t registe r (lfsr) to the sta t e o f the scram b ling lfsr. upon achieving synchronization, the incom i ng data is xored by the deciphering lfsr and descram b led. in order to m a intain synchroni zation, the descram b ler continuously monitors the validity of the unscram bled data that it generates. to ensure this, a link state m onitor and a hold tim e r are used to constantly monitor the synchroni zation status. upon synchronizatio n of the descram b ler the hold tim er starts a 722 us countdown. u pon detection of at least 6 idle sy m bols (30 consecu tive ?1?) within the 722 us period, the hold tim er will reset an d be gin a new countdown. this monitoring operation will continu e indefinitely given a properly operati ng network connection with good signal integ r ity. if the link state m onitor does not reco gnize at least 6 unscram bled idle symbols within 722 us period, the descram b ler will be f o rc ed out of the curren t sta t e of synchr onization an d reset in or der to r e -ac quire synchronization. symbol alig nment the sym bol alignm ent circuit in the ADM7008 determ ines code word alignm ent by recognizing the /j/k delim iter pair. this circu it op erate s on unaligned data f r om the descram b ler . once the /j/k sym bol pair (11000 10001) is detected, subse quent data is aligned on a fixed boundary. symbol decoding infineon-admtek co ltd 3-4 the sym bol decoder functions as a look-up table that translates incom i ng 5b sym bols into 4b nibbles as shown in table 3-1. the sym bol decoder first dete cts the /j /k s y m bol pair preceded by idle sym bols and replaces th e sym bol wi th mac pre a m b le . all subsequent 5b sy m bols are converted to the corresponding 4b nibbles for the duration of th e entire packet. this conversion ceases upon the detection of the /t /r symbol pair denoting the end of stream deli m iter (esd). the trans l ated d a ta is presented on the internal rxd[3:0] signal lines with rxd[ 0] represents the leas t sig n if icant bit of the trans l ated n i bble.
ADM7008 function description pcs code-gro up [4 : 0 ] na me mii (txd/r xd) <3:0> interpretation 1111 0 0 0 0 0 0 d a t a 0 0100 1 1 0 0 0 1 d a t a 1 1010 0 2 0 0 1 0 d a t a 2 1010 1 3 0 0 1 1 d a t a 3 0101 0 4 0 1 0 0 d a t a 4 0101 1 5 0 1 0 1 d a t a 5 0111 0 6 0 1 1 0 d a t a 6 0111 1 7 0 1 1 1 d a t a 7 1001 0 8 1 0 0 0 d a t a 8 1001 1 9 1 0 0 1 d a t a 9 1011 0 a 1 0 1 0 d a t a a 1011 1 b 1 0 1 1 d a t a b 1101 0 c 1 1 0 0 d a t a c 1101 1 d 1 1 0 1 d a t a d 1110 0 e 1 1 1 0 d a t a e 1110 1 f 1 1 1 1 d a t a f 1111 1 i u n d e f i n e d i d l e used as inter-stream fill code 1100 0 j 0101 start-of-stream delimiter, part 1 of 2; alway s used in pairs with k 1000 1 k 0101 start-of-stream delimiter, part 2 of 2; alway s used in pairs with j 0110 1 t u n d e f i n e d start-of-strea m delimiter, part 1 of 2; alway s used in pairs with r 0 1 1 1 r u n d e f i n e d start-of-stream delimiter, part 2 of 2; alway s used in pairs with t 0010 0 h u n d e f i n e d transm i t e r r o r ; used to force signaling errors 0000 0 v u n d e f i n e d i n v a l i d c o d e 0000 1 v u n d e f i n e d i n v a l i d c o d e 0001 0 v u n d e f i n e d i n v a l i d c o d e 0001 1 v u n d e f i n e d i n v a l i d c o d e 0010 1 v u n d e f i n e d i n v a l i d c o d e 0011 0 v u n d e f i n e d i n v a l i d c o d e 0100 0 v u n d e f i n e d i n v a l i d c o d e 0110 0 v u n d e f i n e d i n v a l i d c o d e 1000 0 v u n d e f i n e d i n v a l i d c o d e 1100 1 v u n d e f i n e d i n v a l i d c o d e infineon-admtek co ltd 3-5 table 3-1 lo ok-up t a ble for tr ansla t ing 5b sy mbols into 4b nibbles.
ADM7008 function description valid data signal the valid data signal (rxdv) indicat es that recovered and decoded ni bbles are being presented on the intern al rxd[3:0] synchronous to receive clo c k , rxcl k. rxdv is as serted wh en the first nib b le of trans l ated /j /k is ready f o r transf er over the in tern a l mii. it rem a ins activ e un til eithe r the /t/r delim iter is recognized, link test indicates failure, or no signal is detected. on any of t h ese conditions, rxdv is deasserted. receive err o rs the rxer signal is used to communi cate receiv er error con d itions. w h ile th e receiver is in a state of holding rxdv asserted, the rxer will be asserted for each code word that does not m a p to a valid code-group. 100base-x link monitor the 100base-x link m o nitor functio n allows the receiver to ensure that reliab l e data is being received. w ithout reliable data re ception, the link m onitor will halt bo th transm it and receive operations until such tim e that a valid lin k is detected . the ADM7008 perform s the link integrity test as outlined in ieee 100bas e-x (clause 24) link monitor sta t e diagram . the link status is m u ltiplexe d with 10 mbits/s lin k status to f o rm the reportable link status bit in serial managem e nt re gister 1h, and driven to the lnkact pin. when persistent signal energy is detected on the network, the logic m o ves into a link-ready state after approxim ately 500 us, and waits for an enable from the auto negotiation m odule. w h en receive, the link-up state is en tered, and the tran sm ission and recep tion log i c b l ocks becom e active. s hould auto negotiation be disabled, the link integrity logic m ove s immedi ately to the link-up state after entering the link-ready s t ate. carrier sen s e carrier sense (crs) for 100 mbits/s operation is asserted upon the detect ion of two noncontiguous zeros occurring within a ny 10-bit boundary of the received data stream . the carrier sense function is inde pendent of sym bol alignm ent. in s w itch m ode, crs is asserted during either packet tran sm ission or reception. f o r re peater mode, crs is asserted o n ly during p acket reception. when the id le sym bol p a ir is detected in the received data stream , crs is d easserted. in repeater m o de, crs is only asserted due to receiv e activity. crs is intended to encapsulate rxdv. bad ssd detection a bad start of stream delim iter (bad ssd) is an error condition that occurs in the 100base-x receiver if carrier is detected (c rs a sserted) and a valid /j/k set of code-group (ssd) is not received. if this condition is detected, th en th e ADM7008 will assert r x er and present rxd[3:0] = 1110 to th e intern al mii for the cycles hat correspond to receive d 5b code-groups until at least two idle code- groups are detected. once at least two idle code groups are detected, rxer and crs become deasserted. infineon-admtek co ltd 3-6
ADM7008 function description far-end fa ult auto negotiation prov id es a m echanism f o r trans f erring inf o r m ation f r om the local s t ation to the link partner that a rem o te fault has occurred for 100b ase-tx. as auto nego tiation is not currently speci fi ed for operat i on over fi ber, t h e far end fa u lt indication function (fefi) provides this cap a bility for 100base-fx applications. a rem o te f a ult is an er ro r in the link that one s t ati on can detect while the othe r cannot. an exa m ple of this is a d i s c onnected wire at a s t ation? s trans m itte r. this sta tion will be rece iving valid d a ta and detect th at the link is good via the link integrity m onitor, but will not be able to detect that its transm ission is not propag ating to the other station. a 100base-fx station that detects s u ch a rem o te fault m a y modify its transm itted id le stream from all ones to a group of 84 ones followed by a single 0. this is referred to as the fefi idle pattern. the fefi function is controlled by b it 3 of register 11h. it is initia lized to 1 (encod ed) if the s elfx pin is at logic high level during power on reset. if the fe fi f unction is enabled the ADM7008 will halt a ll cur r ent ope rations and tra n sm it the fefi idle p a ttern when fosd signal is de-a ss erted following a good link indication from the link integrity m o nitor. fosd signal is generated internally f r om the internal sign al detect c i rcu i t. transm is sion of the fefi idle pattern will continue until lin k up signal is asserted. if three or m o re fefi idle patterns are detect ed by the ADM7008, then bit 4 of the basic m ode status register (addr ess 1h) is se t to one un til re ad by m a nagem e nt. additionally, upon detection of far end fault, all receiv e a nd transm it mii activ ity is disab l ed/ignored. 3.1.3 100base-tx transmitter ADM7008 imple m ents a tp-pmd com p liant transceive r for 100base-t x operation. the differentia l transm it driver is shared by the 10base-t and 100base-tx subsystem s . this arrangem ent results in one device that uses the sam e e x ternal m a gnetics for both the 10base-t and the 100base-tx transm ission with sim p le rc com p onent connecti ons. the individually wave-shaped 10base-t and 100base-tx transm it signals are m u l tiplexed in the transm ission output driver selection. ADM7008 100base-tx transm ission driver imple m e nts mlt-3 translation and wave-shaping functions. the rise/fall tim e of th e output signal is closely controlle d to conform t o the target range specified in the ansi tp-pmd stan dard. 3.1.4 100base-fx receiver signal is received th roug h pecl receiver inpu ts from fiber transceiver, an d directly passed to clock recovery circuit for data/clock recovery. sc ram b ler/de-scram bler is bypassed in 100base-fx. automatic ? s ignal_dete ct? functio n block infineon-admtek co ltd 3-7 due to pin lim itation, ADM7008 doesn?t support sdp/sdn in fiber m o de, which is used to connect to fiber transceiver to indicate there is signal on th e fiber. instead, ADM7008 use the data on rxp/rxn to detect co nsecutiv e 65 ?1? on the receiv e data (recovered from rxp/rxn) to determ ine whethe r ?signal? is detected or not. w h en the dete ct co ndition is tr ue (consecu tive 65 bits ?1?), inte rna l sign al detect signa l will be asse rted to inform receive re la tiv e block s to be ready fo r com i ng receive activities.
ADM7008 function description 3.1.5 100base-fx transmitter in 100base fx transm it, the serial data stream is dr iven out as nrzi pecl signals, w h ich enters fiber transceiver in differential-pairs form . fiber tr ansceiver should be av ailable working at 3.3v environm ent. 3.1.6 10base-t module the 10base-t transceiver module is ieee 802.3 com p lia nt. it inclu d es the receiver, transmitter, collision, heartbeat, loopback, jabb er, waveshaper, and link integrity functions, as defined in the standard. f i gure 3-3 provides an overview for the 10base-t module. the ADM7008 10base-t m odule is com p rise d of the following functional blocks: ? ? ? ? ? ? ?
ADM7008 function description the harm oni cs in the transm ission si gnal are attenuated properly. 3.1.10 smart squelch the s m art squelch circuit is responsible for determ in ing when valid data is present on the differential receiv e . t h e ADM7008 im ple m e n ts an intelligent receiv e squelch o n the rxp/rxn differential inputs to ensure that im pulse noise on the receive inputs will not be m i staken for a valid signal. the squelch circuitry em ploys a com b ination of am plit ude and tim ing m easurem ents (a s spec if ied in the ieee 802.3 10base-t standard) to determ ine the va lidity of data on the twisted-pair inputs. the signal at the start of the packet is checked by the analog squelch circuit and any pulses not exceeding the squelch level (e ithe r positiv e or nega tive, d e pending up on polarity) will be rejected. once this f i rst sque lch level is ove r c om e correctly, the opp osite squ e lc h level m u st then be exc eeded within 150n s. finally, the signal m u st exceed the orig in al s quelch lev e l within an additional 15 0ns to ensure th at the input wavefor m will not be rejected. only af ter a ll th ese con d itions have been satisf ied will a co ntrol signa l be genera te d to indicate to the rem a inder of the circu itr y that va lid data is p r ese n t. valid data is considered to be present until the sque lch level has not been generated for a tim e longer than 200 ns, indicating end of packet. once good da ta has been detected, the squelch levels are reduced to m i ni m i ze the effect of noise, causing prem ature end-of-packet detection. the re ceive squelch threshold level can be lowered for use in l onger cable applications. this is achieved by setting bit 7 of register address 10h. 3.1.11 carrier sen s e carrier sens e (crs) is asserted due to receiv e activity once valid data is d e tected via the sm art squelch function. f o r 10 mbps half duplex operation, crs is asserted during either packet transm ission or reception. for 10 mbp s full duplex and repeater m ode operations, th e crs is asserted on ly d u e to receiv e activ ity . infineon-admtek co ltd 3-9
ADM7008 function description figure 3-3 1 0 ba se -t blo ck diagr a m and da ta pa th 3.1.12 collision d e tection the smii d o es not h a ve a collis ion pin. collis ion is de tec t e d inte rnal to the mac, which is g e n e rated by an and function of txen and crs derived fro m txd and rxd, re spectively. the internal mii will still gen e rate the col signal, but this inf o rm ation is no t p a ssed to the amc via the smii. 3.1.13 jabber function the jabber function m o nitors the ADM7008 output and disables the transm itter if it attem p ts to transm it a longer than legal sized packet. if txen is high for greater than 24m s , the 10base-t transm itter will be dis a bled. once disabled by the jabber function, th e transm itter stays disabled for the entire tim e that the txen signal is asser t ed. this signal has to be deasser t ed f o r approximately 408 m s (the un-jab tim e ) before the jabber functio n re-enables the transm it outputs. the jabber function can be disabled by programm i ng bit 0 of register address 10h to high. 3.1.14 link test f unction a link pulse is used to check the integrity of the connection with the remote end. if valid link pulses are not rec e ived, the link detecto r disables th e 10base-t twisted-pa ir transm itte r, receiv e r, and collision detection functions. the link pulse generator produces pulses as defi ned in ieee 802.3 1 0 base-t standard. each lin k pulse is no m i nally 100ns in duration and is transm itted every 16 m s , in the absence of transm it data. setting bit 10 of register 10h to high can disable link pulse check function. infineon-admtek co ltd 3-10 m ii t o s m ii c o nvert er rxd sm ii t o mi i c o n v ert e r syn c syn c tx d rec eiv e fi lter cr s rx d [ 3 : 0] rx d v co l rxcl k rxp rx n tx e n tx e r t x d [ 3:0] tx c l k wave sh a p er 10 /1 00 t x dr i v e r tx p tx n pl l cl o c k ph ase ge ne ra t o r 1 0 bas e- t r e c e iv er 10b as e- t t r a n sm it t e r m i i to 1m 8 m a n c h es t er co de en code r n r z t o nrzi 1m8 t o m i i m a nch e s t e r co de dec o d e r smart s q u e lth filt er testm d
ADM7008 function description 3.1.15 automatic link polarity detection ADM7008?s 10base-t transceiver module incorporates an ?autom a tic link polarity detection circuit?. the inver t e d polar ity is dete rm ined when seven consecutive link pulse s of inverted pol a r ity or th ree consecutive packets are receiv e d with inverted end-of-packet pulses. if the input polarity is rev e rsed, the er ror con d ition will b e autom a tica lly cor r ec ted and reported in bit 13 of register 11h. 3.1.16 clock synthesiz er the ADM7008 im ple m ents a clock synthesizer that gene rates all the reference clocks needed from a single external frequency source. the clock sour ce m u st be a ttl level signal at 25 mhz +/- 50pp m . 3.1.17 auto negotiation the auto negotiation function provides a m echan is m for exchanging configuration inform ation between two ends of a link segm e n t and autom a tica lly selecting the highest perform a nce mode of operation supported by both de vices. fast link pulse (flp) bu rsts provide the signaling used to communicate auto negotiation ab ilities between two devices at each end of a link segm ent. for furth e r detail regarding auto negotiation, refer to clau se 28 of the ie ee 802.3u specification. the ADM7008 supports four different ethernet protocols, so the in clusion of auto negotiation ensures that the highest perform a nce protocol will be selected based on the ability of the link partner. the auto negotiation function within the ADM7008 can be controlled either by in ternal register access or by the use of configuration pins are sam p led. if disabled, auto negotiation will not occur until sof t ware en ables b it 12 in reg i ste r 0. if auto negotia tion is enab led, the negotiation proce s s will commence immediately. when auto negotiation is enabled, the ADM7008 tran sm its the abilities progr ammed into the auto negotiation advertisem ent register at address 04h via flp bursts. any combination of 10 mbits/s, 100 mbits/s, half duplex and full duplex m odes m a y be selected. auto ne gotiation controls the exchange of configuration inform a tion. u pon successfully auto nego tiation, th e abilities rep o rted by th e link partner are stored in the au to negotiation link partner abili ty register at address 05h. the contents of the ?auto negotiation link partner ab ility r e giste r ? are u s ed to auto m a tically co nf igure to the highest perform a nce protocol between the lo cal and far-end nodes. software can de term ine which m ode has been configured by auto negotiati on by com p aring the contents of register 04h and 05h and then selecting the technology whose bit is set in both registers of highest priority relative to the f o llowin g list. 1. 100base-tx full duplex (highest priority) 2. 100base-tx half duplex 3. 10base-t full duplex 4. 10base-t half duplex (lowest priority) infineon-admtek co ltd 3-11 the basic mode control register at address 0h provides control of en abling, disabling, and restarting of the auto negotiation function. w h en auto negotiati on is disabled, the speed selection bit (bit 13) controls switching between 10 mbps or 100 mbps opera tion, while the duplex m ode bit (bit 8) controls switching between full duplex operation and half dupl ex operation. the speed selection and duplex
ADM7008 function description mode bits have no effect on the m ode of operation wh en the au to negotiatio n enable bit (bit 12 ) is s e t. the basic mode status register at address 1h indicates th e set of available abili ties for technology types (bit 15 to bit 11), auto negotiation ability (bit 3), and extended register capability (bit 0). these bits are hardwired to indicate the fu ll functionality of the ADM7008. the bm sr also pro v ides status on : 1.w hether auto negotia tio n is com p lete (bit 5 ) 2.whether the link partner is advertising th at a remote fault has occurred (bit 4 ) 3.whether a valid link has been established (bit 2) the auto negotiation ad vertisem ent regis t er at addre ss 4h indicates the auto ne gotiation abilities to be advertised b y the ADM7008. all availab l e ab ilities are transm itted by default, b u t writing to this register or configuring external pins can suppress any ability. the auto negotiation link partner ab ility register at address 05h indi cates the abilities of the link partner as indicated by auto negotiation comm unication. t h e contents of this register are considered valid when the auto negotiation com p lete bits (bit 5, register address 1h and bit 4, register 17h) is set. 3.1.18 auto negotiation and speed configuration the twelve sets of four pins listed in table 3- 2 configure the speed capability o f each channel of ADM7008. the logic state of these pins is latched into the advertisem ent register (register address 4h) for auto negotiation purpose. these pins are also used for evaluating the default value in the base mode control register (registe r 0h) according to t a ble 3-2. infineon-admtek co ltd 3-12
ADM7008 function description 3.2 mac interface the ADM7008 interfaces to eigh t 10/100 med i a acce ss c ontrollers (mac) via the rmii, smii, or source synchronous smii (ss_smii) interface. all ports on the device operate in th e sam e interface mode that is selected. 3.2.1 reduced media independent interface (rmii) the reduced m e dia independent in terface (rmii) is com p liant to the r m ii conso r tium ? s rmii rev . 1.2 specification. the refclk pin that supplies th e 50 mhz reference clock to the ADM7008 is used as the rmi i refclk signal. all rmii s i gnals with the e x ception of the as ser tion of crsdv_p are synchronous to refclk. see figure 3-4 figure 3-4 rmii signal diagram 3.2.2 receive path for 100m figure 3-5 shows the relationship am ong refc lk, crsdv_p , rxd0_p , rxd1_p and rxer_p while receiving a valid packet. carrier sense is dete cted, which causes crsdv_p to assert asynchronou sly to refclk. the receiv e d data is then placed into th e fifo for resynchron ization. after a m i nimum of 12 bits are p l aced into the fi fo, the received data is presen ted onto rxd[1:0]_p synchronous ly to refclk. note that while th e fi fo is filling up rxd[1:0]_p is set to 00 until the first received di-bit of pream ble (01) is presented onto rxd[1:0]_p . w h en carri er sense is de-asserted at th e end o f a packet, crsdv_p is de-asserted when the f i rst d i -bit o f a nibble is presen ted o n to rxd[1:0]_p synchronously to refclk . if there is still data in the fifo that has not yet been presented onto rxd[1:0]_p , then on th e second di-bit of a nibble, crsdv _p reasserts. this pattern of assertion an d de-ass ertion continu e s until all received data in th e fifo has been presen ted onto rxd[1:0]_p . infineon-admtek co ltd 3-13 mac ph y tx en tx d 0 tx d 1 crs dv rx d 0 rx d 1 re f c lk
ADM7008 function description ref c l k rx d crsd v 00 00 00 00 00 00 01 01 01 01 01 11 dat a dat a rx e r c a rrie r s e ns e det e c t e d pr ea m b l e sf d ca r r i e r de ass e r t ed da ta dat a da ta da ta da ta dat a dat a dat a 00 00 00 figure 3-5 rmii recep tion withou t error 3.2.3 receive path for 10m figure 3-6 1 0 m rmii rec e iv e diagra m in 10m mode, rxer_p will m a intain low all the tim e due to fa lse carrie r and sy mbol erro r is not supported b y 10m mode. dif f erent from 100m m ode, rxd_p and crsdv_p can trans ition on ce per 10 refclk cycles. after carrier sense is de-asserted y e t the fi fo data is not fu lly presented onto rxd_p , the crsdv_p d e -asse rtion and re-assertion al so f o llo ws this ru le. infineon-admtek co ltd 3-14 ref c l k rx d cr sdv 00 00 dat a t r an si ti on o n c e e v e r y 10 cy cl e s 01 dat a dat a p r ea m b l e / s f d trans i t i on o n c e ev ery 10 c y c l e s
ADM7008 function description 3.2.4 transmit p a th for 100m figure 3-7 shows the relationship among refclk, txen _p and txd[1:0]_p during a transm it event. txen_p and txd[1:0]_p are synchr onous to refclk. when txen_p is asserted, it indicates that txd[ 1:0] _p contains v a lid da ta to be trans m itted. w h en txen_p is d e -as s erted, valu e on txd[1:0]_p should be ignored. if an odd number of di-bits are presented onto txd[1:0]_p and txen_p , the final di-b it will be discarded by ad2106. figure 3-7 1 00m rmii tr ansmit diag r a m 3.2.5 transmit p a th for 10m in 10mbse-t m ode, each di-bit m u st be rep eated 10 tim es by the mac, txen_p and txd[1:0]_p should be synchronous to refclk. w h en txen_p is asserted, it indicates th at data on txd[1:0]_p is valid for transm ission. in 10base-t m ode, it is possible that the number of pream b le bits and the number of fram e bit s receiv e d are not integ e r nibbles. the pream b le is always padded up su ch that th e s f d appears on the rmii aligned to the nibble boundary . extra bits at th e end of the fra m e that do not com p lete a nibble are truncated by ad2106. figure 12 shows the tim i ng diagram for 10m t r ansm ission. figure 3-8 1 0 m rmii tra n smit diagr a m infineon-admtek co ltd 3-15 ref c l k t xd_ p tx e n _ p 00 00 d a t a tr a n s i t i on on c e ev e r y 10 c y cles 01 da t a da t a p r ea m b l e /s f d t r a n s i t i o n on ce eve r y 10 cy cl es ref c l k tx d [ 1 : 0 ] tx e n 00 00 01 01 01 01 01 11 data data data data data data data data da t a 00 00 00 pr e a m b l e sf d data 01 01 01 01
ADM7008 function description recommend v a lue auto ne gotiation capability anend is rec _ 10 m tp_fullduple x e n abl e di sa bl e 10 0 ful l 10 0 hal f 10 ful l 10 h a l f 0 0 1 9 9 9 9 9 0 0 0 9 9 9 0 1 1 9 9 9 0 1 0 9 9 1 0 1 9 9 1 0 0 9 9 1 1 1 9 9 1 1 0 9 9 table 3-2 ch annel con f ig uration 3.2.6 serial and source synchronous media independent interface the synchronous media independent in terface (smii) conf orm s to th e smii specif ication rev . 2.1. the refclk pin that supplies the 125mhz refe rence clock to the ADM7008 is used as the smii/serial and source synchronous media ind e pendent in terface (ss_ smii) reference clock. all smii/ss _ smii signals are synchronous to re fc lk. the dif f erences between smii and ss_smii are 1. smii shares the sam e sync signal from mac yet ss_smii take tx_sync signal as synchronization input for transm ission and output rx_sync to mac for reception sy nchronizatio n usage. 2. smii use refclk (125mhz) fo r both receive and transmit bloc ks. ss_smii takes txclk as transm it block reference clock and output an 125m hz rxclk to m a c for receive usage. all signals output from ADM7008 are synchronous to rxclk. in this m o de, refclk will be div i ded by 5 to generate 25 m clock before it is fed into ADM7008 intern al pl l block. ss_smii m o de is enable d by setting rsmode1 (pin 43) to low and pla c ing a pull up resistor on cr sdv_p6. in this m o d e , crsdv_ p[3] beco mes rx_sync, crsdv_p4 becom e s rxclk and txen_p4 a c ts as tx_sync. infineon-admtek co ltd 3-16
ADM7008 function description figure 3-9 smii signal diagram figure 3-10 ss_smii sig n al diagram 3.2.7 100m receive path received data and con t rol inform ation is grouped in 10-bit segm ents that are d e lim ited by the s ync signal in s m ii m ode (or sync_rx in ss_smii m ode ) as shown in figure 15. each segm ent represents a new byte of data. figure 3-11 100m smii receiv e timing diagram in ss_smii m ode, refclk and sync are no longe r common for bot h transm it and receive blocks. they are renam e d to rxclk and rx_sync. figure 3-12 100m ss_s m ii receiv e timing diagram in smii m o de, when rxdv bit is high, rxd[7:0] are used to convey packet data; when rxdv bit is infineon-admtek co ltd 3-17 re f c l k r xd_ p sync r xd7 cr s r xdv rx d 0 r xd1 rx d 2 r xd3 rx d 4 rx d 6 r xd7 r xd5 cr s r xdv r xd0 r xd1 r xd2 r xd3 r xd4 r xd6 r xd7 r xd5 cr s r xdv r xd0 r xd1 r xd2 ma c phy sy n c tx d 0 _ p [7 :0 ] r x d0_p[ 7 : 0 ] re f c l k ma c ph y t x c l k_ ss m i i s y nc_ t x t x d0 _ p [7 :0 ] rx cl k _ s s m i i sy n c _r x rx d0 _ p [7 : 0 ] rxclk _ s s m i i rxd _ p sy nc _ r x rx d 7 cr s rx d v rx d 0 rx d 1 rx d 2 rxd3 rxd4 rxd6 rxd7 rxd5 cr s rx d v rxd0 rxd1 rxd2 rxd3 rxd4 rxd 6 rxd 7 rxd 5 cr s rx d v rxd 0 rxd 1 rxd 2
ADM7008 function description low , rxd[7:0] are carrying phy status . see t a ble 3-3 for more detail. c r s rx d v rx d 0 r x d 1 rx d 2 r x d 3 r x d 4 r x d 5 r x d 6 rx d 7 x 0 r x e r f r o m previous f r am e s p eed 0 = 10mb/s 1 = 100mb/s duplex 0 = h a lf 1 = full link 0 = down 1 = up jabber 0 = o . k. 1 = error upper nibble 0 = inv a lid 1 = v a lid fa lse carrier 0 = no 1 = detected 1 x 1 one data by te (t w o m i i dat a nib b le) table 3-3 re ceiv e data encoding for smii/ss_smii mode 3.2.8 10m receiv e path sim ilar to 100m receive path except that each segm ent is r e peated 10 tim e s. the mac can s a m p le any one of every 10 segm ents in 10base-t m o de. the mac also ha s to generate a sync pulse once every 10 clo c k cycles. figure 3-13 10m smii re ceiv e timing diagram figure 3-14 10m ss_smii receiv e timing diagra m infineon-admtek co ltd 3-18 re f c l k r xd_ p s ync rx d7 _ 0 crs_ 1 rx dv_ 1 rx d0 _ 1 rx d1 _ 1 rx d2 _ 1 rx d3 _ 1 rx d4 _ 1 rx d6_ 1 rx d7 _ 1 rx d5_ 1 cr s _ 1 rx dv_ 1 rx d0 _ 1 rx d1 _ 1 rx d2 _ 1 rx d3_ 1 rx d4_ 1 rx d5_ 1 rx d6 _ 1 rx d7 _ 1 cr s _ 2 rx dv_ 2 rx d0 _ 2 data repeat ed 10 t i m e s ( u se 10 s y n c f o r 1 b y te data) r x cl k _ ssm i i rx d _ p sync _ r x rx d7_ 0 cr s _ 1 rx dv_ 1 rx d0 _ 1 rx d1 _ 1 rx d2 _ 1 rx d3 _ 1 rx d4 _ 1 rx d6 _ 1 rx d7_ 1 rx d5 _ 1 crs _ 1 rx dv _ 1 rx d0 _ 1 rx d1 _ 1 rx d2 _ 1 rx d3 _ 1 rx d4 _ 1 rx d5_ 1 rx d6_ 1 rx d7_ 1 crs _ 2 rx dv_ 2 rx d0 _ 2 d a ta re pea te d 10 t i m e s ( u se 10 sy nc_rx fo r 1 b y te d a ta)
ADM7008 function description 3.2.9 100m transmit path sim ilar to 100m receiv e path, transm it data is gr ouped in 10-bit segments that are delim ited by the sync signal (or tx_sync in ss_s mii m ode), ea ch seg m ent repres ents a new byte of data. see figure 3-15 for 100m smii transm it tim ing diagram and figure 3-16 for ss_smii tim i ng diagram. in ss_smii m ode, refclk and sync are no longe r commonly used for both transm it and receive blocks. the y are ren a med to txclk and tx_sync. w h en txen bit is low , data on txd[ 7:0] will be ignored by ADM7008. see t a ble 3-4 tr ansm it data encoding for m o re detail. figure 3-15 100m smii transmit timing diagram figure 3-16 100m ss_s m ii transmit timing diagram 3.2.10 10m transmit path in 10base-t m ode, each segm ent must be rep eated 10 times by the m a c. in this m ode, the mac must generate the sam e data in each of the 10 segm ents. ADM7008 will sam p le the incom i ng data at the 5 th sync (or sync_tx) location. figure 3-17 10m smii transmit timing diagram infineon-admtek co ltd 3-19 re f c l k t xd_ p s ync txd 7 t xer t xen tx d 0 tx d 1 tx d 2 tx d 3 tx d 4 txd 6 txd 7 tx d 5 t xer t xen tx d0 tx d 1 tx d 2 tx d 3 tx d 4 tx d 6 txd 7 tx d 5 t xer t xen tx d0 tx d 1 tx d 2 t x c l k _ ssm i i txd_ p s ync _ t x txd 7 t xer t xen tx d 0 tx d 1 tx d 2 tx d 3 tx d 4 txd 6 txd 7 tx d 5 t xer t xen tx d0 tx d 1 tx d 2 tx d 3 tx d 4 tx d 6 txd 7 tx d 5 t xer t xen tx d0 tx d 1 tx d 2 re f c l k t xd_ p s ync tx d 7 _ 0 tx e r _ 1 tx e n _ 1 tx d 0 _ 1 tx d 1 _ 1 tx d 2 _ 1 tx d 3 _ 1 tx d 4 _ 1 tx d 6 _ 1 tx d 7 _ 1 tx d 5 _ 1 tx e r _ 1 tx e n _ 1 tx d 0 _ 1 tx d 1 _ 1 tx d 2 _ 1 tx d 3 _ 1 tx d 4 _ 1 tx d 5 _ 1 tx d 6 _ 1 tx d 7 _ 1 tx e r _ 2 tx e n _ 2 tx d 0 _ 2 data repeat ed 10 t i m e s ( u se 10 s y n c f o r 1 b y te data)
ADM7008 function description figure 3-18 10m ss_smii transmit timing diagra m 3.3 led display register 19 is used for different m o de led display. there are two kind of led display m echanism s provided by ADM7008: single and dual color l e d m ode, either m ode provides power on led self test to m i nim i ze and ease the sys t em test led cost. 3.3.1 single color led when single color led is programmed (dualled is set to low during power on reset), all ports led will be off during power on reset (output value sam e as recomm end value on led pins). af ter power on reset, all internal parall el leds will b e on for 2 s e conds, in ternal p a rallel led status will be stream ed out through l e d_data and this sig n al is outpu t by ADM7008 at the falling edge of led_clk. before describing the se rial led output data form at, we tend to describe the m eaning of intern al pa ra llel leds. there are three types of led supported by ADM7008 internally. the first is lnkact, which repres ents the status of link and transm it/receive activity; the second is spdled, which indicates the speed status and the last is dupcol, which shows pure dupl ex status in full duplex and duplex/collision com b ined status in half duplex. all these three led can be controlled by register 19 to change display contents. after led self test, table 3-4, 3-5 and 3-6 show the on/off polarity acco r d ing to dif f e rent recomm ended value setting for spdled, dupcol and lnkact. when the recommend value is high, ADM7008 will drive led low ; ADM7008 will drive the led high whe n the recomm end value is low, instead. s p e e d s p d l e d 10m 1 10 0m 0 link fail 1 table 3-4 speed led dis p la y infineon-admtek co ltd 3-20 t x c l k _ ssmi i t xd_ p s ync _ t x t x d7 _ 0 tx e r _ 1 tx e n _ 1 t x d0 _ 1 t x d1 _ 1 t x d2 _ 1 t x d3 _ 1 t x d4 _ 1 t x d6 _ 1 t x d7 _ 1 t x d5 _ 1 tx e r _ 1 tx e n _ 1 t x d0 _ 1 t x d1 _ 1 t x d2 _ 1 t x d3 _ 1 t x d4 _ 1 t x d5 _ 1 t x d6 _ 1 t x d7 _ 1 tx e r _ 2 tx e n _ 2 t x d0 _ 2 da t a r e pe at e d 10 t i m e s ( u se 1 0 s y n c _rx f o r 1 b y t e da t a )
ADM7008 function description du pc ol du ple x h a l f f u l l link up blin k (high) wh en c o llisio n low all th e ti m e link fail high all th e ti m e high all th e ti m e table 3-5 du plex led dis p la y link/activi ty speed l i n k a c t i v i t y lin k up lo w blink ( h ig h) whe n r x /tx link fail high all th e ti m e high all th e ti m e table 3-6 ac tiv i t y /link l e d displa y 3.3.2 dual color led when dual color led is program m e d (dualled is set to high during power on reset), all ports led will be of f during power on reset (out put high on lnkact and spdled and outpu t recomm end value on d u pcol). after power on reset, all leds will be on for 1 s e conds to test 10m mode lnkact/spdled connection and on fo r another 1 second to test 100m mode lnkact/spdled wire connection. this period a llow manufacture o p erato r to check whether the led wire connection on pcb board is correct or not. after led self-tes t, table 3-7 and table 3-8 s how the on/off polarity according to different speed detected by ADM7008. dupcol is alwa ys set to single color m ode display no m a tter the value of dual led is. s p e e d s p d l e d 10m 0 10 0m 1 link fail 0 table 3-7 speed led dis p la y lnk act speed l i n k a c t i v i t y 10 0m l i nk u p lo w b l i nk ( h ig h) whe n r x / t x 1 0 m link _up h i gh blin k (low ) w h en rx /tx link fail low all th e ti me low all th e ti me infineon-admtek co ltd 3-21 table 3-8 ac tiv i t y /link l e d displa y
ADM7008 function description 3.3.3 serial ou tput led status internal le d status will be stream e d output through two pins ? led_data and led_clk, where led_data is used to indicate internal 8 por t l e d status and synchronous to led_clk. figure 3-19 stream led under rmii mode the high duration for l e d_clk is 40ns and the low dur ation is 600ns to form 640ns period clock. ADM7008 will burst 24 bit status in one tim e in order to disp lay in ternal link/activity, duplex/collision and speed sta t us. w h en a burst is com p leted, led_clk will keep low f o r 40 m s and system can use it to di stinguish between two bursts. 3.4 management register access the smi consists of two pins, managem e nt data clock (mdc) and m a nage m e nt data input/output (mdio). the adm7 008 is designed to support an mdc frequency specified in the ieee specification of up to 2.5 mhz. the mdio line is bi-directional and m a y be sha r ed by up to 32 devices. the mdio pin requires a 1.5 k ? pull-up which, during idle and tu rnaround periods, will pull mdi o to a logic one state. each mii m a nagem e nt data fr am e is 64 bits long. th e first 32 bits are preamble consisting of 32 contiguous logic one bits on mdio and 32 corresponding cycl es on mdc. following pream ble is the start-of-fram e fiel d indicated by a <01> pattern. th e next field signals the operation code (op) : <10> indicates read from mii m a nagem e nt register operation, and <01> indicates write to mii m a nagem e nt register operation. the next two fields are phy device address and mii m a nage m e nt register address. both of the m are 5 b its wide and the m o s t significant bit is transferred fi rst . during read operation, a 2-bit tu rn around (ta) tim e spacing between the register address field and data field is provided for the md io to avoid contention. following the turnaround tim e , a 16-bit data stream is read from or written into th e mii m a nagem e nt registers of the ADM7008. 3.4.1 preamble s uppression the ADM7008 supports a pream bl e suppression m ode as i ndicated by an 1 in bit 6 of the basic m ode status regis t er (regis ter 1h). if the station managem e nt entity (i.e. ma c or other m a nagem e nt controller) determ ines that all phys in the system support pream ble suppression by reading a 1 in this bit, then the station m a nagem e nt entity needs not ge nerate pre a m b le for each m a nagement trans a ction. infineon-admtek co ltd 3-22 le d _ c l k le d _ d a t a dup c o l 0 du p c o l 1 du p c o l 2 du p c o l 3 du p c o l 4 du p c o l 5 du p c o l 6 du p c o l 7 du p c o l 0 spe e d0 spe e d1 spe e d2 spe e d3 spe e d4 spe e d5 spe e d6 spe e d7 ln kac t 0 ln kac t 1 ln kac t 2 ln kac t 3 l n kac t 4 l n kac t 5 l n kac t 6 l n kac t 7
ADM7008 function description the ADM7008 requires a single in itialization sequen ce of 32 bits of pream b le following powerup/hardware reset. this requirem ent is ge nerally met by pulling-up th e resistor of mdio. while the a d m7008 will respond to m a nage m e nt accesse s without preamble, a m i nimum of one idle bit between m a nage m e nt transactions is required as specified in ieee 802.3u. when adm 7008 detects that there is phys ical address m a tch, then it will enable read/w r ite capability for extern al access. w h en neither p hysical addr ess nor reg i ster address is m a tched, then ADM7008 will tri- sta t e the mdio pin. figure 3-20 smi read o p era t ion 3.4.2 reset operation the ADM7008 can be reset either by hardware or software. a hard ware reset is accom p lished by applying a negative pulse, with duration of at least 100 m s to the rst_n pin of the ADM7008 during norm a l operation to gu arante e inte rnal power on reset circuit is re s e t well. sof t ware res e t is activa t ed by setting the r e set bit in th e basic m ode contro l reg i ste r (bit 15, regis t er 0h ). this bit is self- clear ing and , when set, will re turn a value of 1 un til the sof t ware rese t o p eration has com p leted, please note tha t internal sram will not be r e set dur ing s o f t ware rese t. figure 3-21 smi write o p era t ion hardware re set ope ratio n sam p les the pins and initializes a ll r e gis t ers to their def a ult va lues. this process includes re-evaluation of all hardware configurable registers. a hardware re set affects all the eight phys in the device. a software reset can reset an individual phy and it does not latch th e externa l p i ns nor res e t the registers to their respective default value. logic levels on severa l i/o pins are detec t ed during a hardware re set to dete r m ine the initia l functionality of ADM7008. som e of these pins are used as output ports after reset operation. infineon-admtek co ltd 3-23 md c mdi o ( m a c ) m d i o (p hy) z 0 1 1 0 0 1 1 0 0 0 0 0 0 0 z 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 z pream bl e s t a r t op c o d e ( r e ad) phy add r es s ( 5 ' h0c i n t h i s ex am pl e ) r egi s t er a d dr es s ( 5 'h0 0 i n t h i s ex am pl e ) t a regi st er d a t a (16' h 1300 in t h i s ex am pl e) md c mdi o ( m a c ) z 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 z pream bl e s t a r t op c o d e (w ri t e ) phy add r es s ( 5 ' h0c i n t h i s ex am pl e ) r egi s t er a d dr es s ( 5 'h0 0 i n t h i s ex am pl e ) t a regi st er d a t a (16' h 1300 in t h i s ex am pl e) 0
ADM7008 function description care m u st be taken to ensure th at the configura tion s e tup will not interfer e with n o rm al operation. dedicated c onf iguration pins can be tied to vcc or ground directly. conf iguratio n pins m u ltiplexed with logic level output functions should be either weakly pulled up or weakly pulled down through resis t ors. c onfiguration pins m u ltiplexed with l e d outputs should be set up w ith on e of the following circuits shown in figure 3-21. 3.5 pow e r management there are two types of power saving m ode pr ovided by ADM7008: receive power saving (so called medium de tect power saving) and transm it powe r saving mode (so called low power link pulse power saving m ode). 3.5.1 medium detect pow er saving an analog block is designed for carrier sense detect ing. when there is no ca rrier sense presented on m e dium (cable not attached), then ?signal detect? will not be o n . w h enev er cable is attached to ADM7008 and the vo ltage thresh old is above +/- 50m v, then sd will be asse rted high to indicate that there is cable attached to ADM7008. al l intern al blocks except managem e nt block will be disabled (reset) before s d is asserted. w h en sd is asse rted, in terna l auto negotiation bl ock will be turned on and the 10m transm it driver will also be turned on f o r auto neg o tiation pro cess. auto negotiation will issue control s i gn als to control 10m receive and 100m a/d block acco rding to d i fferent state in arbitr ation block diag ram. during auto negotiation, all digital blocks except m a nage m e nt and li nk m onitor blocks will be disabled to reduce power consum ption. whenever operating speed is determ ined (either auto negotiation is on or off), the non-active spee d relative circuit will be disabled all the tim e to save m o re power. for exam ple, when corresponding port is operating on 10m, then 100m relative blocks will be disabled and 10m relative blocks will be disabled wh enever corresponding port is in 100 m m ode. auto negotiation block will be reset when sd signal goes from high to low. see figure 3-22 for the state diagram for this algorithm . 3.5.2 transmit p o w er saving in ADM7008, enabling tx power saving feature could save transm it power before any link partner trying to link up. two transm it powe r saving m e thods are applied to ADM7008 by register 17.5 configuration. w h en setting register 17.5 to ?0?, the transm it- driver will lower the driving current all the tim e to save power before the receiver dete cts signals coming in. w h e n setting to ?1?, ADM7008 transm it low-power link pulse (l lp) to the cable. the waveform of llp is the sam e as nlp and flp, the difference is the period of llp is around 100m s . besides the longer period, ADM7008 also lower the tra n sm it-drivin g curren t between sendin g a pulse and a pulse. t h e tx powe r saving feature is activated by setting ADM7008 of n-way or 10m cap abilities. see figure 3-23 for reference. infineon-admtek co ltd 3-24
ADM7008 function description figure 3-22 medium de tect po w e r m a nagem e nt flo w char t another way to redu ce instan t pow er is to sep a rate the l e d di splay period. all 24 leds will be divided in to 24 tim e fram e and each tim e fram e occupi es 1 u s . one and only one led will be driven at each tim e fram e to red u ce instan t current consu m ed from led. infineon-admtek co ltd 3-25 idle disall = 1 encardet = 1 carrier ? yes sd = 1 enanen = 1 pwr_rst || software_rst auto negotiation process yes no
ADM7008 function description figure 3-23 lo w po w e r link pulse during tx for po w e r man a gement 3.6 voltage regulator ADM7008 requires two different levels, 3.3v and 1.8v, of voltage supply to provide the power to different parts of circuitry insi de the chip. ADM7008 has a build-in voltage regulator circuitry to generate the 1.8v voltage from 3.3v power source. ther efore, an external pnp pow er transistor is also needed and the block diagram of voltage regulator is shown as below. infineon-admtek co ltd 3-26 flp = 80 m a (an) nlp = 80 m a (10m ) m l t3 = 40 m a (10 0 m ) drv on = 1 pw _ save_ tx = o ff o r m edi um det ec t = on or for c e _ good_li nk=on i n 10 m o r forc e i n 100m m ode pw _ save_ tx = o n a n d m e di um det ec t = off and (a ut o negi at i on enabl e = on or fo rc e i n 10m m ode ) and force_good_li nk =o ff if 10 m m ode nlp = 60 m a (10 m ) flp = 60 m a (a n ) drv on = 0 rg16drv 62m a = off llp = 20 m a or 60 m a (a n or 10m ) drv on = 0 rg16d rv 62m a = on id l e tx pw savin g mo d e
ADM7008 function description figure 3-24 extern al pnp po w e r tr a n sistor diag ram infineon-admtek co ltd 3-27 r1 r2 b a nd- gap r e f e r e nce v o l t a ge gener a t o r v ref co n t r o l v 3. 3 v v re f v 1. 8v r2 r1 + r 2 i n t e r n al c i r cui t of r egul at or pn p p o w e r tr an si st or v 1. 8v
ADM7008 register description chapter 4 register description note: please refer to section ? 1.5.2 register type descriptions ? for an explanation of pin abbrevia tion s . 4.1 register mapping infineon-admtek co ltd 4-1 a d d r e s s r e g i s t e r n a m e d e f a u l t 0 h c o n t r o l r e g i s t e r 3 1 0 0 1 h s t a t u s r e g i s t e r 7 8 4 9 2h ? 3h phy identifier register 2h=002e, 3h=cc23 002e, cc23 4h auto negotiation advertisem ent register 01e1 5h auto negotiation link p a rtner ability register 01e1 6h auto negotiation expansion register 0004 7h - fh reserved reserved 10h phy control register 1000 11h phy 10m configuration register 0008 12h phy 100m configuration register 0022 13h led configuration register 0a34 14h interrupt enable register 03ff 16h phy generic status register 0000 17h phy specifi c status register 0060 18h recomm end value storage register 0000 19h global interrupt st atus register 0000 1dh receive error counter 0000 1eh chip id register ?at? 8818 1fh global interrupt register (o nly available in port 0) 0000
ADM7008 register description 4.2 register bit mapping 4.2.1 register #0h -- control register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 r s t l p b k spd_ l a n e n p d n i s o rstar d p l x coltst spdmsb 0 0 0 0 0 0 r/w r/w r / w r / w r / w r/ w r/w p i n r / w r/w r o r o r o r o r o r o 4.2.2 register #1h ? status register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 capt4 t x f u l t x h a l f t f u l t h a l f c a p t 2 0 0 0 mfsup ancomp rmflt a n e n l i n k j a b extcap r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.2.3 register #2h ? phy id register (002e) 4.2.4 register #3h ? phy id register (cc11) 4.2.5 register #4h ? advertisement register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 n p a g e 0 r f 0 as m_d i r pa u s e t 4 fd x 1 0 0 h d x 100 fd x 1 0 h d x 1 0 0 0 0 0 1 r/w r o r / w r o r / w r/w r o r/w r/w r / w r / w r o r o r o r o r o 4.2.6 register #5h ? link partner ability register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 n p a g e a c k r f 0 l p _d i r l p _pa u l p _t 4 l p _fd x l p _h d x l p _f1 0 l p _h 1 0 0 0 0 0 1 r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.2.7 register #6h ? auto ne gotiation expansion register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 p d f l t l p n p a b n p a b l e p g r c v lpanab r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.2.8 register #7h ? # fh re served 4.2.9 register #10h ? phy configuration register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 i f s e l 0 0 0 0 0 0 0 0 0 0 xoven 0 0 0 dispmg r o r o r o r o r o r o r o r o r o r o r o r/w r/w r/w r o r/w infineon-admtek co ltd 4-2
ADM7008 register description 4.2.10 register #11h ? 10m configuration register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 drv62ma a p d i s e n r j a b distj a b n t h fgdlnk r o r o r o r o r o r o r o r o r o r o r/w r/w r / w r/w r / w r/w 4.2.11 register #12h ? 100m configuration register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 se l f x 0 0 disscr e nfefi 0 1 0 r o r o r o r o r o r o r o r o r/w r o r o r / w r/w r o r o r o 4.2.12 register #13h ? led configuration register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 lnkc3 lnkc2 lnkc1 l nkc0 dupc3 dupc2 dupc1 dupc0 spdc3 spdc2 spdc1 spdc0 r o r o r o r o r/w r/w r/w r/w r/w r / w r / w r / w r/w r/w r/w r / w 4.2.13 register #14h ? interrupt enable register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 xovc hg s p d c h g dup c h g p gr c h g l nkc h g s y mer r fcar four u n t j ab i n t r j ab i n t r o r o r o r o r o r o r/w r/w r/w r / w r / w r / w r/w r/w r/w r / w 4.2.14 register #16h ? phy generic s t atus register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 0 c b b r k brk1 brk0 m d f x e n xover cblen7 cblen 6 cblen5 cblen4 cblen3 cblen2 cblen1 cblen0 r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.2.15 register #17h ? phy specific status register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 j a b r x j a b t x polar p auout p a u i n duplex s p e e d l i n k r e c p a u r e c d u p r e c s p d recan r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.2.16 register #18h ? recommend value storage register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 pw r d n r e c a n s e l f x rec1 00 re c f u l p a u r e c disfefi xoven xover r m ii_s m ii repeat er phya4 phya3 p h y a 2 p h y a 1 p h y a 0 r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.2.17 register #19h ? int errupt status register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 xovc hg s p d c h g dup c h g p gr c h g l nkc h g s y mer r fcar four u n t j ab i n t r j ab i n t r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o infineon-admtek co ltd 4-3
ADM7008 register description 4.2.18 register #1 dh ? receive error counter 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 e r b 1 5 e r b 1 4 e r b 1 3 e r b 1 2 e r b 1 1 e r b 1 0 e r b 9 e r b 8 e r b 7 e r b 6 e r b 5 e r b 4 e r b 3 e r b 2 e r b 1 e r b 0 r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.2.19 register #1eh ? chip id (8888 ) 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 cid 3 3 cid 3 2 c i d 3 1 c i d 3 0 c i d 2 3 cid 2 2 cid 2 1 cid 2 0 cid 1 3 c i d 1 2 c i d 1 1 c i d 1 0 cid 0 3 cid 0 2 cid 0 1 c i d 0 0 r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.2.20 register #1 fh ?total in terrupt sta t us (only for port 0) 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 i n t 7 i n t 6 i n t 5 i n t 4 in t 3 in t 2 in t 1 in t 0 0 0 0 0 0 0 0 0 r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.3 register description 4.3.1 control (register 0h ) infineon-admtek co ltd 4-4 bit # name description type default interface 1 5 r s t r ese t 1: phy res e t 0: norm al operation setting this bit in itiates the sof t ware reset function that resets the selected port, except for the phase-locked loop circuit. it will re -la t ch in all hardware configuration pin values. the software reset process takes 25us to com p lete. this bit, which is self-clearing, returns a value of 1 until the re set process is com p lete. r/ w sc 0 h 1 . u p d a t e d b y mdc/mdio. 2.connect to central control block to generate reset signal. 1 4 l p b k b ack enable 1:enable loop back m ode 0: disable l oop back mode this bit controls the phy loop back operation that isolates the network transm itter o u tputs (txp and txn) and routes the m ii transm it data to the m ii receiv e data path. this function sho u ld onl y be used when auto ne g otia tion is r/ w 0 h 1 . u p d a t e d b y mdc/mdio only. control the w i re connection in driver
ADM7008 register description bit # name description type default interface infineon-admtek co ltd 4-5 disabled (bit12 = 0). the specific p hy (10base-t or 100base-x ) used for this operation is determ ined by bits 12 and 13. 1 3 s p e e d _ l s b speed selection lsb 0.60.13 0 0 10 mbps 0 1 100 mbps 1 0 1000 mbps 1 1 reserved link speed is selected by this bit or by auto negotiation if bit 12 of this register is set (in wh ich case, the value of this bit is ignored). r/ w 1 h w h e n a u t o n egotiation is enable, th is pin has no effect. 1 2 a n e n a uto negotiation enable 1: enable auto negotiation process 0: disable a u to negotiation process this bit de te rm ines whether the link speed should set up by the auto negotiation process or not. it is set at p ower up or reset if the p i _recanen p in detec t s a logic 1 inpu t leve l in twisted-pair mode. r/ w 1h this bit anded with pi_recanen p in dete rm ines auto negotiation capability of phy841f. 1 1 p d n p ower down enable 1: power down 0: norm al operation ored result with pi_pwrdn pin. setting this bit high or asserting the pi_pw r dn puts the ph y841f into p ower down m ode. during the power down m ode, txp/txn and all led outputs are tri-s t ated and the mii/rm ii interfaces are isolated. r/ w 0 h 1 . o n l y access through mdc/mdio 1 0 i s o i solate phy841f from network 1: isolate p hy from mii/rmii 0: norm al operation setting this control b it is olates the pa rt from the rmii/mii, with the exception of the serial m a nagem e nt interface. w h en this bit is asserted, the p hy841f does not respond to t xd, txen and txer inputs, and it presents a high im pedence on its txc, rxc, crs dv, rxer, rxd, col and crs outputs. r/ w 0 h 1 . o n l y access through mdc/mdio 2.used to reset corresponding port.
ADM7008 register description bit # name description type default interface 9 a n e n _ rs t r estart auto negotiation 1: restart auto negotiation process 0: norm al operation setting this bit while auto negotia tio n is enabled forces a new auto negotiation p rocess to start. this b i t is self -c lea r ing and returns to 0 afte r the auto negotiation p rocess has commenced. r/ w sc 0 h 8 d p l x d uplex mode 1: full duplex m ode 0: half duplex m ode if auto negotiation is disabled, this bit determ ines the duplex mode for the link. r/ w 1h this bit ored with recf ul p in dete rm ines the duplex capability of phy841f when anen disa bled. 7 c o l t s t collision te st 1: enable c o l signal test 0: disable c o l signal test w h en set, th is bit will c a u se the col signal of mii interface to be asserted in response to the assertion of txen. r/ w 0 h 6 s p e e d _ m sb speed selection msb set to 0 all the tim e indicate th at th e phy841f does not support 1000 mbps function. r o 0 h a l w a y s 0 . 5 : 0 r e s e r v e d n ot applicable ro 00h always 0. 4.3.2 status (register 1h ) infineon-admtek co ltd 4-6 bit # name description type default interface 1 5 c a p _ t 4 100base-t4 capable set to 0 all the tim e to indicate that the phy841f does not support 100base-t4 r o 0 h 1 4 c a p _ t x f 100base-x full duplex capable set to 1 all the tim e to indicate that the phy841f does support full duplex mode r o 1 h 1 3 c a p _ t x h 100base-x half duplex capable set to 1 all the tim e to indicate that the phy841f does support half duplex m ode r o 1 h 1 2 c a p _ t f 10m full d uplex capable tp : set to 1 all th e tim e to indic a te that the phy841f does support 10m full duplex m o de fx : set to 0 all th e tim e to indic a te that r o 1 h
ADM7008 register description bit # name description type default interface infineon-admtek co ltd 4-7 the phy841f does not support 10m full duplex m o de 1 1 c a p _ t h 10m half duplex capable tp : set to 1 all th e tim e to indic a te that the phy841f does support 10m half duplex m o de fx : set to 0 all th e tim e to indic a te that the phy841f does not support 10m half duplex m o de r o 1 h 1 0 c a p _ t 2 100base-t2 capable set to 0 all the tim e to indicate that the phy841f does not support 100base-t2 r o 0 h 9 : 7 r e s e r v e d n ot applicable r o 0 h 6 c a p _ s u p r mf preamble suppression capable this bit is h a rdwired to 1 indica ting that the phy841f accepts m a nagem e nt fram e without preamble. minimum 32 pre a m b le bits are required following power-on or hardware reset. one idle bit is required b etween any two m a nagem e nt transactions as per ieee 802.3u specification. ro 1h use to control mdc/mdio state ma chine. 5 a n _ c o mp a uto negotiation complete 1: auto negotiation process com p leted 0: auto negotiation process not com p leted if auto negotiation is enabled, this bit indicates whether th e auto negotiation p rocess has been com p leted or not. set to 0 all the tim e when fiber mod e is selected. r o 0 h status u p d a t e d by auto n egotiation control block. 4 r e s e r v e d n ot applicable r o 0 h 3 c a p _ a n e g a uto negotiation abilit y 1: capable of auto negotiation 0: not capable of auto negotiation tp : this bit is set to 1 all the tim e , indicating that phy 841f is capable of auto negotiation. fx : this bit is se t to 0 a ll the tim e, indicating that phy841f is not capable of auto negotiation in fiber mode. r o 1 h 2 l i n k l ink status 1: link is up 0: link is down this bit reflects th e current state of the lin k -tes t-fail state m achine. loss of a valid link caus e s a 0 latched in to this b it. i t ro, ll 0h updated by per p ort link monitor
ADM7008 register description bit # name description type default interface rem a ins 0 until this register is re ad b y the serial m a nagem e nt interface. w h enever linkup, this bit should be read twice to get link up status 1 j a b j abber detect 1: jabber condition detected 0: jabber condition not detected ro, lh 0h updated by per p ort jabber detector 0 e x t r e g e xtended capability 1: extended register set 0: no extended register set this bit def a ults to 1, ind i cating tha t the phy841f i m ple m ents extended registers. r o 1 h 4.3.3 phy identifier register (register 2h) bit # name description type default interface 1 5 : 0 p h y - id[15:0] ieee address ro 002e rg2_phy_i d input 4.3.4 phy identifier register (register 3h) bit # name description type default interface 1 5 : 1 0 p h y - id[15:0] ieee address/model no./rev. no. ro cc10 rg3_phy_ i d input 9 : 4 m o d e l [ 5 : 0] infineon- admtek co ltd phy revision id. r o c c 1 0 rg3_model_i d input 3 : 0 r e v - id[3: 0 ] infineon- admtek co ltd phy revision id. r o 4 h 0 rev_id i n p u t 4.3.5 advertisement (register 4h) infineon-admtek co ltd 4-8 bit # name description type default interface 1 5 n p n e xt page this bit is d e f a ults to 1, indica ting th at phy841f is next page capable. r/ w 0 h 1 4 r e s e r v e d n ot applicable ro 0h 1 3 r f r emote fault 1 rem o te fault has been detected 0 no remote fault has been detected this bit is written by serial m a nage ment interface for the purpose of communicating the r e m o te f a ult condition to the auto ne g otiation link r/ w 0h s/ w should read status from register 1 (bit 1.4) and fill out this bit dur in g auto negotiation in case remote
ADM7008 register description bit # name description type default interface infineon-admtek co ltd 4-9 p artne r . fault is d e te cted. 1 2 r e s e r v e d n ot applicable ro 0h 1 1 a s m _ d i r a symmetric pause direc tion bit[11:10] capability 00 no pause 01 symm etric pause 10 asymm e tric pause toward link partner 11 both symm etric pause and asy m m e tric pause to ward local dev i ce r/ w 0h 1 0 p a u s e p ause operation for full duplex value on paurec will be sto r ed in this bit during power on reset. r/ w p i n p i _ p a u r e c 9 t 4 technology ability for 1 00base-t4 def a ults to 0. r o 0 h 8 t x _ f d x 100base-tx full duplex 1: capable of 100m full duplex operation 0: not capable of 100m full duplex operation r/ w 1h used by auto n egotiation block 7 t x _ h d x 100base-tx half duplex 1: capable of 100m operation 0: not capable of 100m operation r/ w 1h used by auto n egotiation block 6 1 0 _ f d x 10base-t full duplex 1: capable of 10m full duplex operation 0: not capable of 10m full duplex operation r/ w 1h used by auto n egotiation block 5 1 0 _ h d x 10base-t half duplex 1: capable of 10m operation 0: not capable of 10m operation r/ w 1h used by auto n egotiation block n ote: that bit 8:5 should be com b ined with rec100, recful pin input to determ ine th e finalized speed and duplex mode. 4 : 0 s e l e c t o r field these 5 bits are hardwired to 00001b, indicating that the phy841f supports ro 01h used by auto n egotiation
ADM7008 register description bit # name description type default interface ieee 802.3 csma/cd. block. 4.3.6 auto negotiation lin k partner ability (register 5h) bit # name description type default interface 1 5 n p a g e n ext page 1: capable of next page function 0: not capable of next page function ro 0h updated by auto n egotiation block 1 4 a c k a cknowledge 1: link partner acknowledges reception of the ability data word 0: not acknowledged ro 0h updated by auto n egotiation block 1 3 r f r emote fault 1: rem o te fault has been detected 0: no rem o t e fault has been detected ro 0h updated by auto n egotiation block 1 2 r e s e r v e d n ot applicable ro 0h 1 1 l p _ d i r l ink partner asymmetric pause d irection. ro 0h updated by auto n egotiation block 1 0 l p _ p a u l ink partner pause capability value on paurec will be sto r ed in this bit during power on reset. ro 0h updated by auto n egotiation block 9 l p _ t 4 l ink partner technology ability for 100base-t4 def a ults to 0. ro 0h updated by auto n egotiation block 8 l p _ f d x 100base-tx full duplex 1: capable of 100m full duplex operation 0: not capable of 100m full duplex operation ro 1h used by auto n egotiation block 7 l p _ h d x 100base-tx half duplex 1: capable of 100m operation 0: not capable of 100m operation ro 1h used by auto n egotiation block 6 l p _ f 1 0 10base-t full duplex 1: capable of 10m full duplex operation 0: not capable of 10m full duplex operation ro 1h used by auto n egotiation block 5 l p _ h 1 0 10base-t half duplex 1: capable of 10m operation 0: not capable of 10m operation ro 1h used by auto n egotiation block 4 : 0 s e l e c t o r field e ncoding definitions. ro 01h updated by auto n egotiation block. infineon-admtek co ltd 4-10
ADM7008 register description 4.3.7 auto negotiation expansion register (register 6h) bit # name description type default interface 1 5 : 5 r e s e r v e d n ot applicable ro 000h 000h 4 p f a u l t p arallel detection fault 1: fault has been detected 0: no fault detect ro, lh 0h updated by auto n egotiation block 3 l p n p a b l e link partner next page able 1: link partner is next page capable 0: link partner is not next page capable ro 0h updated by auto n egotiation block 2 n p a b l e n ext p age able 0: next page disable 1: next page enable. r o 1 h 1 p g r c v p age received 1: a new page has been receiv e d 0: no new page has been receiv e d ro, lh 0 h u p d a t e d b y auto n egotiation block 0 l p a n a b l e l ink partne r auto negotiation able 1: link partner is auto negotiable 0: link partner is not auto negotiable r o 0 h u p d a t e d b y auto n egotiation block 4.3.8 register reserved (register 7h -fh) bit # name description type default interface 1 5 : 0 r e s e r v e d n ot applicable 4.3.9 generic p h y configuration register (register 10h) note: phy control/configuration r e gister s start from address 16 to 21. bit # name description type default interfac e 15:5 reserved n ot applicable r o 1 h 1 4 x o v e n cross over auto detect enable. 0: disable 1: enable r/ w p i n p i _ x o v e n 3:1 reserved n ot applicable r o 0 h 0 d i s p m g d isable power management feature. 0: enable. enable medium detect function. 1: disable. medium _on is high all the tim e. r/ w 0 h r e c _ d i s p m g infineon-admtek co ltd 4-11
ADM7008 register description 4.3.10 phy 10m module configurat ion register (register 11h) bit # name description type default interfac e 1 5 : 6 r e s e r v e d n ot applicable ro 0h 5 d r v 6 2 m a r educe 10m driver to 62ma. 1: 62ma 0: norm al r/w 0h w ill be on when disp mg is set to low during power on reset. 4 a p d i s a uto polarity disable 1: auto polarity function disabled 0: norm al r/ w 0 h r e c _ a p o l dis tp module polarity pin. 3 e n r j a b e nable receive jabber monitor. 0: disable 1: enable r/ w 1 h r e c _ e n rj a b control two blocks : 1.receive jab b er (crs keeps high all the tim e) 2.crs lo w less than 2 3 us 2 d i s t j a b d isab l e transmit jabber 1: disable t r ansm it jabber function 0: enable transm it jabber function r/ w 0 h r e c _ d i s t j a b 1 n t h n ormal threshold 0: lower 10base-t re ceive threshold 1: norm al 10base-t receive thres hold r/ w 0 h r e c _ n t h 0 f g d l n k f orce 10m receive goo d link 1: force good link 0: norm al operation r/ w 0 h r e c _ f gdl ink 4.3.11 phy 100m module control register (register 12h) infineon-admtek co ltd 4-12 bit # name description type default interfac e 1 5 : 8 r e s e r v e d n ot applicable ro 0h 7 s e l f x f iber sele ct 1: fiber mode 0: tp mode r/ w p i n ~ p i _ s e l t p 6 : 5 r e s e r v e d n ot applicable r/ w 1h 4 d i s s c r d isable scramble r 1: disable s c ram b ler 0: enable scram b ler when set to fiber m ode, this bit will be r/ w p i n w h e n p rogram m ed to fiber m ode, set to 1 autom a tically
ADM7008 register description bit # name description type default interfac e f o rced to 1 a u tom a tically . w r ite 0 to this bit in fiber mode has no effect. 3 e n f e f i e nable fef i 1: enable f e fi 0: disable f e fi r/ w p i n ~ d i s f e f i ored resu lt of enfefi and ftpre n 2 r e s e r v e d n ot applicable ro 0h 1 r e s e r v e d n ot applicable r/ w 1h 0 r e s e r v e d n ot applicable r/ w 0h 4.3.12 led configuration register (register 13h) infineon-admtek co ltd 4-13 bit # name description type default interfac e 1 5 : 1 4 r e s e r v e d n ot applicable ro 0h 1 3 : 1 2 r e s e r v e d n ot applicable ro 00 1 1 : 8 l n k c t r l l ink/act le d control. 0000: collis ion 0001: all errors 0010: duplex 0011: duplex/collis ion 0100: speed 0101: link 0110: transm it activity 0111: receive activity 1000: tx/rx activity 1001: link/receive activity 1010: link and tx/rx activity 1011: 100m false carrier error/10m receive jab b er 1100: 100m error end of stream /10m transm it jabber 1101: 100m sym bol error 1110: distance (see le d description for more detail) 1111: cable broken distance r o 1 0 1 0 rec_lnkled_ ctrl 7 : 4 d u p c t r l d uplex led control. 0000: collis ion 0001: all errors 0010: duplex 0011: duplex/collis ion 0100: speed 0101: link 0110: transm it activity 0111: receive activity r o 0 0 1 1 rec_dupled_ ctrl
ADM7008 register description bit # name description type default interfac e 1000: tx/rx activity 1001: link/receive activity 1010: link and tx/rx activity 1011: 100m false carrier error/10m receive jab b er 1100: 100m error end of stream /10m transm it jabber 1101: 100m sym bol error 1110: distance (see le d description for more detail) 1111: cable broken distance 3 : 0 s p d c t r l speed led control. 0000: collis ion 0001: all errors 0010: duplex 0011: duplex/collis ion 0100: speed 0101: link 0110: transm it activity 0111: receive activity 1000: tx/rx activity 1001: link/receive activity 1010: link and tx/rx activity 1011: 100m false carrier error/10m receive jab b er 1100: 100m error end of stream /10m transm it jabber 1101: 100m sym bol error 1110: distance (see le d description for more detail) 1111: cable broken distance r o 0 1 0 0 rec_spdled_ ctrl 4.3.13 interrupt e n able register (register 14h) infineon-admtek co ltd 4-14 bit # name description type default interfac e 1 5 : 1 0 r e s e r v e d n ot applicable ro 00h 9 x o v c h g cross over mode changed interrupt e nable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 8 s p d c h g speed changed interrupt enable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 7 d u p c h g d uplex changed interrupt enable r/ w 1 h
ADM7008 register description bit # name description type default interfac e 1: inte rrup t enable 0: inte rrup t disable 6 p g r c h g p age received interrupt enable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 5 l n k c h g l ink status changed interrupt enable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 4 s y m e r r symbol error interrupt e nable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 3 f c a r f alse carrier interrupt enable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 2 t j a b i n t transmit jabber interrupt enable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 1 r j a b i n t r eceive jab b er interrup t enable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 0 e s d e r r e rror end of stream enable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 4.3.14 phy generic status register (register 16h) note: phy status registers start from 22 to 28 (29 to 30 reserves for further use) infineon-admtek co ltd 4-15 bit # name description type default interfac e 1 5 : 1 4 r e s e r v e d n ot applicable ro 00h 1 3 c b b r k 4.3.4 phy identifier re gister (registe r 3h) 0: connection properly 1: broken r o 0 h 1 2 : 1 1 r e s e r v e d n ot applicable ro 0h 1 0 m d m edium detect. real time status fo r medium_detect signal 0: medium _detect fail 1: medium _detect pass r o 0 h 9 f x e n f iber enable. only changed when ph y r eset 0: tx 1: fx m ode or?ed result of pi _ selfx and 17.9 r o p i n p i _ s e l f x
ADM7008 register description bit # name description type default interfac e (selfx) 8 x o v e r cross over status. 0: mdi m o de 1: mdix mode r o 0 h 7 : 0 r e s e r v e d n ot applicable ro 00h 4.3.15 phy specific status register (register 17h) bit # name description type default interfac e 1 5 : 1 2 r e s e r v e d n ot applicable ro 0h force to 0 all the tim e. 1 1 j a b - r x r eal time 10m receive jabber statu s 1: jabber 0: no jabber r o 0 h 1 0 j a b _ t x r eal time 10m transmit jabber status 1:jabber 0: no jabber ro 0h updated by 10m block 9 polar p olarity. only available in 10m 0: norm al polarity 1: polarity r e versed r o 0 h 8 p a u o u t p ause out capability. disabled when hal f duplex. 0: lack of pause out capability 1: has paus e out capability r o 0 h 7 p a u i n p ause in capability. disabled when half duplex. 0: lack of pause in capability 1: has paus e in capab ility r o 0 h 6 d u p l e x operating duplex 1: full duplex 0: half duplex r o 1 h 5 s p e e d operating s p eed 1: 100mb/s 0: 10mb/s r o 1 h 4 l i n k r eal time link status 1: link up 0: link down r o 0 h 3 r e c p a u p ause recommend value. only changed when phy reset. this bit is d i sab l e d r o p i n p i _ p a u r e c infineon-admtek co ltd 4-16
ADM7008 register description bit # name description type default interfac e autom a tically when recdup is 0. 0: pause disable 1: pause enable 2 r e c d u p d uplex recommended value. only changed when phy res e t 1: full duplex 0: half duplex r o p i n p i _ d u p f u l 1 r e c s p d speed reco mmend value. only changed when phy reset 1: 100m 0: 10m r o p i n p i _ r e c 1 0 0 0 r e c a n e n r ecommended auto n egotiation value . only changed when phy reset r o p i n p i _ r e c a n e n 4.3.16 phy recommend value status register (register 18h ) infineon-admtek co ltd 4-17 bit # name description type default interfac e 1 5 p w e d n p ower down status r o p i n 1 4 r e c a n a uto negotiation recom m end value r o p i n 1 3 s e l f x f iber select recommend value r o p i n 1 2 r e c 1 0 0 speed reco mmend value 0: 10m 1: 100m r o p i n 1 1 r e c f u l d uplex recommend value. 0: half duplex 1: full duplex r o p i n 1 0 p a u r e c p ause capability recom m end value 1: pause enable 0: pause disable r o p i n 9 r e s e r v e d n ot applicable ro pin 8 x o v e n cross over capability r ecommend value. 0: disable 1: enable r o p i n 7 x o v e r cross over status. 0: non-cross over 1: cross over r o 0 h 6 r m i i _ s m i i r mii_smii inter f ace 1: rmii or smii in terfa ce used 0: non rmii_smii interface r o p i n 5 r e s e r v e d n ot applicable ro pin
ADM7008 register description bit # name description type default interfac e 4 : 0 p h y a p hy address r o 0 h 4.3.17 interrupt s t atus register (register 19h) bit # name description type default interfac e 1 5 : 1 0 r e s e r v e d n ot applicable cor 00h 9 x o v c h g cross over mode changed 1: cross over m ode cha nged 0: cross over m ode not changed cor 0 h u p d a t e d b y pmd block 2 8 s p d c h g speed changed 1: speed changed 0: speed not changed cor 0h updated by auto n egotiation block 7 d u p c h g d uplex changed 1: duplex changed 0: duplex not changed cor 0h updated by auto n egotiation block 6 p g r c h g p age received 1: page received 0: page not received cor 0h updated by auto n egotiation block 5 l n k c h g l ink status changed 1:link status changed 0: link status not changed cor 0h updated by auto n egotiation block 4 s y m e r r symbol error 1: sym bol error 0: no sym b ol error cor 0 h u p d a t e d b y 100m block 3 f c a r f alse carrie r 1: false car r ier 0: no false carrier n ote: high whenever link is failed . cor 0 h u p d a t e d b y 100m block 2 t j a b i n t transmit jabber 1: jabber 0: no jabber cor 0h updated by 10m block 1 r j a b i n t r eceive jab b e r 1: jabber 0: no jabber cor 0h updated by 10m block 0 e s d e r r e rror end of stream 1: esd error 0: no esd error cor 0 h u p d a t e d b y 100m block 4.3.18 receive error counter register (register 1dh) infineon-admtek co ltd 4-18 bit # name description type default interfac e 1 5 : 0 e r b [ 1 5 : 0 ] e rror counter. includes 1.100m false carrier 2.100m sym b ol error 3.10m transm it jabber r o 0 0 0 0 h
ADM7008 register description bit # name description type default interfac e 4.10m receiv e jabber 5.error sta r t o f stream 6.error end of stream 4.3.19 chip id re gister (register 1fh) bit(s) name description r/w default interfac e 1 5 : 0 c h i p i d [ 1 5 : 0] infineon-admtek co ltd chip id ro 8818 4.3.20 per port interrupt and revisi on id register (register 1eh) bit # name description type default interfac e 15:8 i n t p [ 7 : 0 ] p e r p o r t i n terr upt status. only available in port 0. 1 - interrupt asserted in corresponding port 0 - interrupt not asserted in corresponding p ort r o 8 ? h 0 0 7 : 0 r e s e r v e d n ot applicable ro 8?h00 infineon-admtek co ltd 4-19
ADM7008 electrical specification chapter 5 electrical specification 5.1 dc characteri z a tion 5.1.1 absolute maximum rating symbol parameter rating units v cc33 3.3v power supply 3.0 to 3.6 v v cc18 1.8v power supply 1.62 to 1.98 v v in input voltage -0.3 to v cc3 3 + 0.3 v vout output voltage -0.3 to vcc 33 + 0.3 v tstg storage temperature -55 to 155 c pd power dissipation 1.85 w esd esd rating 2000 v table 5-1 electrical absol u te ma ximum rating 5.1.2 recommen d ed operating conditions symbol parameter m i n t y p max units vcc 33 power supply 3.135 3.3 3.465 v vin input voltage 0 - vcc v tj junction operating temperature 0 25 115 c table 5-2 re commended opera t ing conditions 5.1.3 dc electrical characterist ics for 3.3v operation (under vcc=3.0v~3.6v, tj= 0 c ~ 115 c ) symbol parameter conditions m i n t y p max units vil input low voltage cmos 0.3 * vcc v vih input high voltage cmos 0.7 * vcc v vol output low voltage cmos 0.4 v voh output high voltage cmos 2.3 v ri input pull_up/down resistance vil=0v or vih = vcc 7 5 k ? infineon admtek co ltd 5-1 table 5-3 dc electrical charac teris t ic s for 3.3v o p era t ion
ADM7008 electrical specification 5.2 ac characteri z a tion 5.2.1 xi/osci (crystal/oscilla tor) timing figure 5-1 cr y s tal/oscillator timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_xi_per xi/osci clock period 40.0 - 50ppm 4 0 . 0 4 0 . 0 + 50pp m ns t_xi_hi xi/osci clock high 1 4 2 0 . 0 ns t_xi_lo xi/osci clock low 1 4 2 0 . 0 ns t_xi_rise xi/osci clock rise tim e , v il (m ax ) to v ih (m in) 4 n s t_xi_fal l xi/osci clock fall tim e , v ih (m in ) to v il (m ax) 4 n s table 5-4 cry s tal/oscilla tor timing infineon admtek co ltd 5-2 t_ x i _ r is e t_ x i _ f all v ih _ x i t _ x i _h i t _x i_lo t_ x i _ p e r v il _ x i
ADM7008 electrical specification 5.3 rmii timing 5.3.1 refclk input timing (whe n refclk_sel is set to 1) figure 5-2 refcl k input timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_in50_per refclk cl ock period 40.0 - 50ppm 4 0 . 0 4 0 . 0 + 50pp m ns t_in50_hi refclk cl ock high 1 4 2 0 . 0 ns t_in50_lo refclk cl ock low 1 4 2 0 . 0 ns t_in50_rise refclk cl ock rise tim e , v il (m ax ) to v ih (m in) 2 n s t_in50_fall refclk cl ock fall tim e , v ih (m in ) to v il (m ax) 2 n s table 5-5 re fcl k input timing infineon admtek co ltd 5-3 t _ i n 50 _r i s e t _ i n 5 0_f a l l v ih _ r mi i t _ i n 5 0_h i t _i n 5 0_l o t _ i n 5 0_p er v il _rmii
ADM7008 electrical specification 5.3.2 refclk output timing (when refclk _sel is set to 0) figure 5-3 refcl k outp ut timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_out50_per refclk cl ock period 40.0 - 50ppm 4 0 . 0 4 0 . 0 + 50pp m ns t_out50_hi refclk cl ock high 1 4 2 0 . 0 26 ns t_out50_lo refclk cl ock low 1 4 2 0 . 0 26 ns t_out50_rise refclk cl ock rise tim e , v il (m ax ) to v ih (m in) 2 n s t_out50_fall refclk cl ock fall tim e , v ih (m in ) to v il (m ax) 2 n s t_out50_jit refclk cl ock jittering (p-p) 0 . 1 5 n s table 5-6 re fcl k outpu t timing infineon admtek co ltd 5-4 t _ o u t5 0_r i s e t_ o u t 5 0 _ f a l l v ih _ r m i i t_ out 5 0 _ hi t _ out5 0 _ lo t_out 5 0 _ p e r v il _r mii
ADM7008 electrical specification 5.3.3 rmii transmit timin g figure 5-4 rmii transmit timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_rt_dsetup txd to refclk rising setup time 2 n s t_rt_dhold txd to re fclk rising hold tim e 2 n s t_rt_txe2mh 1 00 txen asserts to da ta tra n sm it to m e dium 2 3 5 ns t_rt_txe2mh 1 0 txen asserts to da ta tra n sm it to m e dium 1 5 5 0 ns t_rt_txe2ml 10 0 txen de-asserts to f i nis h transm ittin g 2 6 0 ns t_rt_txe2ml 10 txen de-asserts to f i nis h transm ittin g 1 2 5 0 ns table 5-7 rmii transmit timing infineon admtek co ltd 5-5 re fclk tx d pr ea m tx d 0 tx d1 tx d 2 tx d 3 tx d 4 tx d 5 t_ r t _ d setu p tx e n tx d n t_ rt_ d h o l d p r eam 00 dat a on m e d i um t _ r t _t x e 2m h 00 t _ r t _t x e 2m l
ADM7008 electrical specification 5.3.4 rmii receive timing figure 5-5 rmii receiv e timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_rr_mh2 c sh 1 00 signal detected on medium to crsdv high 2 6 5 n s t_rr_mh2 c sh 1 0 signal detected on medium to crsdv high 1 0 0 0 n s t_rr_ml2csl 10 0 idle detected on medium to crsdv low 2 6 0 n s t_rr_ml2csl 10 idle detected on medium to crsdv low 5 7 0 n s t_rr_csh2 dat 100 crsdv high to receive data on rxd 1 6 0 n s 10 crsdv high to receive data on rxd 1 6 0 0 n s t_rr_csl2 dat 100 crsdv toggle to end of data receiving 1 6 0 n s t_rr_csl2 dat 10 crsdv toggle to end of data receiving 1 6 0 0 n s t_rr_ddl y refcl k ri sing to rxd/crsdv de lay tim e 5 n s t_rr_csh2 dat table 5-8 rmii receiv e timing infineon admtek co ltd 5-6 refclk t _ r r _c s l 2d a t cr s d v non_ idl e (in te r n al) t_ rr _ mh2 c s h t_ r r _ m l2 csl rxd p r eam rx d0 rx d1 rx d2 rx d4 rx d5 rx d6 rx dn p r eam 00 t _ rr _ csh2dat t_ r r _ d dl y
ADM7008 electrical specification 5.4 smii clock timing 5.4.1 refclk input timing (when refclk_sel is set to 1) - also apply to tx_clk figure 5-6 refcl k input timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_in125_per refclk/txclk clock period 8.0 - 50ppm 8 . 0 8 . 0 + 50pp m ns t_in125_hi refclk/txclk clock high 2 . 8 4 . 0 n s t_in125_lo refclk/txclk clock low 2 . 8 4 . 0 n s t_in125_rise refclk/txclk clock rise tim e , v il (m a x ) to v ih (m in ) 2 ns t_in125_fall refclk/txclk clock fall tim e , v ih (m in ) to v il (m a x ) 2 ns table 5-9 re fcl k input timing infineon admtek co ltd 5-7 t _ i n 12 5_ r i s e t _ i n 12 5_ f a ll v ih _ s m i i t_ in1 2 5 _ hi t_ in 1 2 5 _ l o t _ i n 12 5_ p e r v il _ s m i i re f c lk
ADM7008 electrical specification 5.4.2 refclk output timing (when refclk _sel is set to 1) also apply to rxclk in ss_smii mode figure 5-7 smii/ss_smii refclk ou tput timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_out125_per refclk cl ock period 8.0 - 50ppm 8 . 0 8 . 0 + 50pp m ns t_out125_hi refclk cl ock high 2 . 4 4 . 0 ns t_out125_lo refclk cl ock low 2 . 4 4 . 0 2 6 ns t_out125_rise refclk cl ock rise tim e , v il (m ax ) to v ih (m in) 2 n s t_out125_fal l refclk cl ock fall tim e , v ih (m in ) to v il (m ax) 2 n s t_out125_jit refclk cl ock jittering (p-p) 0 . 1 5 n s table 5-10 smii/ss_smii refclk ou tput timing infineon admtek co ltd 5-8 t _ o u t 1 25_ r i s e t _ o u t12 5 _ fa ll v ih _ s m i i t _ ou t1 25 _hi t _ou t 1 2 5 _ l o t _ o u t 1 25 _p e r v il _ s m i i re fclk
ADM7008 electrical specification 5.4.3 smii/ss_smii transmit timing figure 5-8 smii/ss_smii transmit ti ming s y m b o l d e s c r i p t i o n m i n t y p max unit t_st_dset u p txd to refclk rising setup time 2 n s t_st_dhold txd to re fclk rising hold tim e 2 n s t_st_txe2mh 10 0 txen asserts to data transm it to m e dium (100m) 3 9 0 ns t_st_txe2mh 10 txen asserts to data transm it to m e dium (10m) 2 3 4 0 ns t_st_txe2ml 10 0 txen de-asserts to finis h transm ittin g (100m) 4 3 0 ns t_st_txe2ml 10 txen de-asserts to f i nis h transm ittin g (10m) 3 8 0 0 ns table 5-11 smii/ss_smii transmit ti ming infineon admtek co ltd 5-9 tx c l k tx d tx er t xen = 1 tx d0 tx d1 0 t _ s t _t x e 2m h sy n c (s mii) t x _ s y n c (ss m ii) 0 t_ st _ d se t u p tx e r t xen = 1 tx er tx e n = 0 t r a n sm it t o m e d i um t_ st _ d ho l d t_ st _ t x e 2 m l
ADM7008 electrical specification 5.4.4 smii/ss_smii receiv e timing figure 5-9 smii/ss_smii rec e iv e timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_sr_mh2csh 10 0 signal detected on medium to crs high (100m) 4 3 0 ns t_sr_mh2csh 10 signal detected on medium to crs high (10m) 6 8 0 ns t_sr_ml2csl 10 0 idle detected on medium to crs l o w (100m) 4 2 0 ns t_sr_ml2csl 10 idle detected on medium to crs l o w (10m) 2 4 0 ns t_sr_mh2dvh 1 00 signal detected on med i um to receive data valid (100m) 4 7 0 ns t_sr_mh2dvh 1 0 signal detected on med i um to receive data valid (10m) 3 8 4 0 ns t_sr_ddl y smi i txcl k rising to sync/rxd delay tim e (smii) 5 ns t_sr_ddl y ss_s mii rxcl k ris i ng to rx_sync/r xd delay tim e (ss_smii) 5 ns table 5-12 smii/ss_smii rec e iv e timing infineon admtek co ltd 5-10 t x c l k (smi i) rx cl k ( ss_ s m i i ) rxd cr s = 1 rx dv = 0 rx d6 fce t_ sr_ d d l y s ync (smi i) rx_sync ( ss_smi i ) rx d7 rx d7 crs = 0 rxdv = 0 non_i d l e (internal) cr s = 1 rx dv = 1 t_ s r _ m h 2 csh t_ sr_ m h2 dv h rx d5 va l i d t_ s r _ m l 2 csl
ADM7008 electrical specification 5.5 serial management interface (mdc/mdio) timing figure 5-10 serial mana gement inter f ac e (m dc/m d io) timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_mdc_per mdc period 1 0 0 ns t_mdc_hi mdc high 4 0 ns t_mdc_lo mdc high 4 0 ns t_mdio_dly mdc to mdio delay tim e 2 0 ns t_mdio_setup mdio input to mdc setup tim e 1 0 ns t_mdio_hold mdio input to mdc hold tim e 1 0 ns table 5-13 serial manage ment inter f a ce (m dc/m d i o ) timing infineon admtek co ltd 5-11 md c mdio( o u tpu t) t_ md i o _ d l y md c m d i o ( i np ut ) t _ m d i o _s etu p t_ md i o _ hol d t_ md c_ l o t_ md c_ p e r t_ mdc _ hi
ADM7008 electrical specification 5.6 pow e r on configuration timing figure 5-11 po w e r on configura t ion timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_v33_v18 3.3v power good to 1.8v power good tbd ms t_v18_rst hardware reset w ith device powered up 2 0 0 ms t_rst_pw hardware reset w ith clock running 8 0 0 ns t_pl_dset u p reset high to configuration setup tim e 2 0 0 ns t_pl_dhold reset high to configuration hold tim e 0 ns table 5-14 po w e r on co nfigura t ion t i ming infineon admtek co ltd 5-12 vcc3 . 3 rst _ n t _ v 18_ r s t re fcl k t_r s t _ pw t_ p l _ d ho l d t_p l _dset u p pw r o n lat c h vcc1 . 8 t _ v 33_ v 1 8
ADM7008 packaging chapter 6 packaging infineon admtek co ltd 6-1 18.5 mm 20.0 +/- 0.1 mm 23.2 +/- 0.2 mm 3.4 mm max 12.5 mm 14.0 +/- 0.1 mm 17.2 +/- 0.2 mm 0.5 mm

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